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CD74HC10M96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HC10M96
Texas Instruments · Logic Gates · SOIC-14
CD74HC10M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 input A of the first 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 2 | 1B | input | Channel 1 input B of the first 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 3 | 2A | input | Channel 2 input A of the second 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 4 | 2B | input | Channel 2 input B of the second 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 5 | 2C | input | Channel 2 input C of the second 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 6 | 2Y | output | Channel 2 output Y of the second NAND gate; balanced CMOS push-pull output that must not be connected directly to VCC or ground, and may be left floating if unused. |
| 7 | GND | power_in | Ground reference pin; the VCC-to-GND bypass capacitor should be placed physically close to this pin. |
| 8 | 3Y | output | Channel 3 output Y of the third NAND gate; balanced CMOS push-pull output that must not be connected directly to VCC or ground, and may be left floating if unused. |
| 9 | 3A | input | Channel 3 input A of the third 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 10 | 3B | input | Channel 3 input B of the third 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 11 | 3C | input | Channel 3 input C of the third 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 12 | 1Y | output | Channel 1 output Y of the first NAND gate; balanced CMOS push-pull output that must not be connected directly to VCC or ground, and may be left floating if unused. |
| 13 | 1C | input | Channel 1 input C of the first 3-input NAND gate (Y = A·B·C); standard CMOS input that must not be left floating. |
| 14 | VCC | power_in | Positive supply; the recommended supply range is 2 V to 6 V, with a 0.1-µF bypass capacitor placed close to this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| High-level input voltage | VIH | 1.5 | V | VCC = 2 V | 4 | ||
| High-level input voltage | VIH | 3.15 | V | VCC = 4.5 V | 4 | ||
| High-level input voltage | VIH | 4.2 | V | VCC = 6 V | 4 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2 V | 4 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V | 4 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC = 6 V | 4 | ||
| Input transition time | tt | 1000 | ns | VCC = 2 V | 4 | ||
| Input transition time | tt | 500 | ns | VCC = 4.5 V | 4 | ||
| Input transition time | tt | 400 | ns | VCC = 6 V | 4 | ||
| Operating free-air temperature | TA | -55 | 125 | °C | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Continuous output current | IO | -25 | 25 | mA | VO > -0.5 V or VO < VCC + 0.5 V | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Lead temperature (soldering 10s) | 300 | °C | SOIC - lead tips only | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| High-level output voltage | VOH | 1.9 | V | VI = VIH or VIL, IOH = -20 µA, VCC = 2 V, TA = -55°C to 125°C | 5 | ||
| High-level output voltage | VOH | 4.4 | V | VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V, TA = -55°C to 125°C | 5 | ||
| High-level output voltage | VOH | 5.9 | V | VI = VIH or VIL, IOH = -20 µA, VCC = 6 V, TA = -55°C to 125°C | 5 | ||
| High-level output voltage | VOH | 3.7 | V | VI = VIH or VIL, IOH = -4 mA, VCC = 4.5 V, TA = -55°C to 125°C | 5 | ||
| High-level output voltage | VOH | 5.2 | V | VI = VIH or VIL, IOH = -5.2 mA, VCC = 6 V, TA = -55°C to 125°C | 5 | ||
| Low-level output voltage | VOL | 0.1 | V | VI = VIH or VIL, IOL = 20 µA, VCC = 2 V, TA = -55°C to 125°C | 5 | ||
| Low-level output voltage | VOL | 0.4 | V | VI = VIH or VIL, IOL = 4 mA, VCC = 4.5 V, TA = -55°C to 125°C | 5 | ||
| Input leakage current | II | -1 | 1 | µA | VI = VCC or 0, VCC = 6 V, TA = -55°C to 125°C | 5 | |
| Input leakage current | II | -0.1 | 0.1 | µA | VI = VCC or 0, VCC = 6 V, TA = 25°C | 5 | |
| Supply current | ICC | 40 | µA | VI = VCC or 0, IO = 0, VCC = 6 V, TA = -55°C to 125°C | 5 | ||
| Supply current | ICC | 20 | µA | VI = VCC or 0, IO = 0, VCC = 6 V, TA = -40°C to 85°C | 5 | ||
| Supply current | ICC | 2 | µA | VI = VCC or 0, IO = 0, VCC = 6 V, TA = 25°C | 5 | ||
| Propagation delay | tpd | 150 | ns | A, B, or C to Y, CL = 50 pF, VCC = 2 V, TA = -55°C to 125°C | 5 | ||
| Propagation delay | tpd | 125 | ns | A, B, or C to Y, CL = 50 pF, VCC = 2 V, TA = -40°C to 85°C | 5 | ||
| Propagation delay | tpd | 100 | ns | A, B, or C to Y, CL = 50 pF, VCC = 2 V, TA = 25°C | 5 | ||
| Propagation delay | tpd | 30 | ns | A, B, or C to Y, CL = 50 pF, VCC = 4.5 V, TA = -55°C to 125°C | 5 | ||
| Propagation delay | tpd | 25 | ns | A, B, or C to Y, CL = 50 pF, VCC = 4.5 V, TA = -40°C to 85°C | 5 | ||
| Propagation delay | tpd | 20 | ns | A, B, or C to Y, CL = 50 pF, VCC = 4.5 V, TA = 25°C | 5 | ||
| Propagation delay | tpd | 26 | ns | A, B, or C to Y, CL = 50 pF, VCC = 6 V, TA = -55°C to 125°C | 5 | ||
| Propagation delay | tpd | 21 | ns | A, B, or C to Y, CL = 50 pF, VCC = 6 V, TA = -40°C to 85°C | 5 | ||
| Propagation delay | tpd | 7 | ns | A, B, or C to Y, CL = 50 pF, VCC = 6 V, TA = 25°C | 5 | ||
| Transition time | tt | 110 | ns | Y, CL = 50 pF, VCC = 2 V, TA = -55°C to 125°C | 6 | ||
| Transition time | tt | 95 | ns | Y, CL = 50 pF, VCC = 2 V, TA = -40°C to 85°C | 6 | ||
| Transition time | tt | 75 | ns | Y, CL = 50 pF, VCC = 2 V, TA = 25°C | 6 | ||
| Transition time | tt | 22 | ns | Y, CL = 50 pF, VCC = 4.5 V, TA = -55°C to 125°C | 6 | ||
| Transition time | tt | 19 | ns | Y, CL = 50 pF, VCC = 4.5 V, TA = -40°C to 85°C | 6 | ||
| Transition time | tt | 15 | ns | Y, CL = 50 pF, VCC = 4.5 V, TA = 25°C | 6 | ||
| Transition time | tt | 16 | ns | Y, CL = 50 pF, VCC = 6 V, TA = -40°C to 85°C | 6 | ||
| Transition time | tt | 13 | ns | Y, CL = 50 pF, VCC = 6 V, TA = 25°C | 6 | ||
| Thermal resistance, junction-to-ambient (D SOIC) | RθJA | 133.6 | °C/W | 5 | |||
| Thermal resistance, junction-to-case (top) (D SOIC) | RθJC(top) | 89 | °C/W | 5 | |||
| Thermal resistance, junction-to-board (D SOIC) | RθJB | 89.5 | °C/W | 5 | |||
| Input capacitance | Ci | 10 | pF | VCC = 5 V | 5 | ||
| Power dissipation capacitance per gate | Cpd | 24 | pF | No load, VCC = 2 V to 6 V | 6 |
CAD (KiCad official)
- Symbol:
CD74HC10M96 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hc10m96-etched.step/cd74hc10m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc10m96.step/cd74hc10m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
605e9d16e12d254f, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).