A4985SETTR-T from Allegro MicroSystems, LLC, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT2B	output	DMOS full bridge 2 output B; motor outputs are rated -2.0 to 37 V and output current ±1 A.
2	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
3	VBB2	power_in	Load supply for bridge 2; operating range 8 to 35 V, absolute maximum 35 V.
4	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
5	ENABLE	input	Logic input; logic high disables all FET outputs and logic low enables them as required, while STEP, DIR, MS1 and MS2 remain active.
6	GND	power_in	Ground; must be tied together with the other GND pins externally to the exposed pad ground plane.
7	CP1	passive	Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
8	CP2	passive	Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
9	VCP	power_out	Charge pump reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBB.
10	VREG	power_out	Internally generated regulator for sink-side FET gates, nominal 7 V; decouple with a 0.22 µF ceramic capacitor to ground.
11	MS1	input	Logic input for microstep resolution select (with MS2), 100 kΩ internal pull-down; changes take effect on the next STEP rising edge.
12	MS2	input	Logic input for microstep resolution select (with MS1), 50 kΩ internal pull-down; changes take effect on the next STEP rising edge.
13	RESET	input	Logic input; when low it sets the translator to the Home state and turns off all FET outputs, and STEP inputs are ignored until it is set high.
14	ROSC	passive	Timing set; tying to VDD, to ground, or through a resistor to ground selects the fixed off-time and decay mode, with tOFF ≈ ROSC / 825 µs for the resistor setting.
15	SLEEP	input	Logic input; logic low puts the device into Sleep mode (under 10 µA), and 1 ms must elapse after leaving Sleep before a STEP command.
16	VDD	power_in	Logic supply; operating range 3.0 to 5.5 V, with 3.3 V and 5 V logic compatibility.
17	STEP	input	Logic input; a low-to-high transition advances the motor one microstep, with minimum high and low pulse widths of 1 µs.
18	REF	input	Gm reference voltage input; reference input voltage range is 0 to 4 V.
19	GND	power_in	Ground; must be tied together with the other GND pins externally to the exposed pad ground plane.
20	DIR	input	Logic input that sets the direction of motor rotation; changes take effect on the next STEP rising edge.
21	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
22	VBB1	power_in	Load supply for bridge 1; operating range 8 to 35 V, absolute maximum 35 V.
23	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
24	OUT1B	output	DMOS full bridge 1 output B; motor outputs are rated -2.0 to 37 V and output current ±1 A.
25	SENSE1	passive	Sense resistor terminal for bridge 1; the SENSE pin voltage must not exceed the 0.5 V maximum rating.
26	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
27	OUT1A	output	DMOS full bridge 1 output A; motor outputs are rated -2.0 to 37 V and output current ±1 A.
28	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
29	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
30	OUT2A	output	DMOS full bridge 2 output A; motor outputs are rated -2.0 to 37 V and output current ±1 A.
31	NC	unconnected	No connection; added between critical output, sense and supply pins on the ET package for no-smoke-no-fire compliance.
32	SENSE2	passive	Sense resistor terminal for bridge 2; the SENSE pin voltage must not exceed the 0.5 V maximum rating.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	QFN-32-EP(5x5)
Category	Power Management ICs
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Load Supply Voltage Range, Operating	VBB	8		35	V	Operating	4
Load Supply Voltage Range, During Sleep Mode	VBB	0		35	V	During Sleep Mode	4
Logic Supply Voltage Range	VDD	3		5.5	V	Operating	4
Output On Resistance, Source Driver	RDS(ON)		700	900	mΩ	Source Driver, IOUT = -800 mA	4
Output On Resistance, Sink Driver	RDS(ON)		700	900	mΩ	Sink Driver, IOUT = 800 mA	4
Body Diode Forward Voltage, Source Diode	VF			1.3	V	Source Diode, IF = -800 mA	4
Body Diode Forward Voltage, Sink Diode	VF			1.3	V	Sink Diode, IF = 800 mA	4
Motor Supply Current, fPWM < 50 kHz	IBB			4	mA	fPWM < 50 kHz	4
Motor Supply Current, Operating, outputs disabled	IBB			2	mA	Operating, outputs disabled	4
Motor Supply Current, Sleep Mode	IBB			10	μA	Sleep Mode	4
Logic Supply Current, fPWM < 50 kHz	IDD			8	mA	fPWM < 50 kHz	4
Logic Supply Current, Outputs off	IDD			5	mA	Outputs off	4
Logic Supply Current, Sleep Mode	IDD			10	μA	Sleep Mode	4
Logic Input Current, high level	IIN(1)	-20		20	µA	VIN = VDD × 0.7	4
Logic Input Current, low level	IIN(0)	-20		20	µA	VIN = VDD × 0.3	4
Logic Input Hysteresis	VHYS(IN)	5	11	19	%	As a % of VDD	4
Blank Time	tBLANK	0.7	1	1.3	μs		4
Fixed Off-Time, OSC = VDD or GND	tOFF	20	30	40	μs	OSC = VDD or GND	4
Fixed Off-Time, ROSC = 25 kΩ	tOFF	23	30	37	μs	ROSC = 25 kΩ	4
Reference Input Voltage Range	VREF	0		4	V		4
Reference Input Current	IREF	-3	0	3	μA		4
Current Trip-Level Error, 38.27% ITripMAX	errI	-15		15	%	VREF = 2 V, %ITripMAX = 38.27%	4
Current Trip-Level Error, 70.71% ITripMAX	errI	-5		5	%	VREF = 2 V, %ITripMAX = 70.71%	4
Current Trip-Level Error, 100.00% ITripMAX	errI	-5		5	%	VREF = 2 V, %ITripMAX = 100.00%	4
Crossover Dead Time	tDT	100	475	800	ns		4
Overcurrent Protection Threshold	IOCPST	1.1			A		5
VDD Undervoltage Lockout	VDDUVLO	2.7	2.8	2.9	V	VDD rising	5
Load Supply Voltage (absolute maximum)	VBB			35	V		2
Output Current (absolute maximum)	IOUT	-1		1	A		2
Logic Input Voltage (absolute maximum)	VIN	-0.3		5.5	V		2
Logic Supply Voltage (absolute maximum)	VDD	-0.3		5.5	V		2
Motor Outputs Voltage (absolute maximum)		-2		37	V		2
Sense Voltage (absolute maximum)	VSENSE	-0.5		0.5	V		2
Reference Voltage (absolute maximum)	VREF			5.5	V		2
Operating Ambient Temperature, Range S	TA	-20		85	°C	Range S	2
Maximum Junction Temperature	TJ(max)			150	°C		2
Storage Temperature	Tstg	-55		150	°C		2
Package Thermal Resistance, ET package (32-contact QFN)	RθJA		32		°C/W	ET package; estimated, on 4-layer PCB, based on JEDEC standard; in still air	5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	for enhanced thermal dissipation, and are lead (Pb) free (suffix -T), with 100% matte-tin-plated leadframes.	2

CAD (KiCad official)

Symbol: A4985SETTR-T
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: a4985settr-t-etched.step / a4985settr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4985settr-t.step / a4985settr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (22 pp, sha256 48496bd05457af8f, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A4985SETTR-T

Verified A4985SETTR-T

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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