component
GBI7A54SMAR
Public Made by Adomby adom
GOSEMICON Gate Drivers, ESOP-8L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownGBI7A54SMAR
GOSEMICON · Gate Drivers · ESOP-8L
GBI7A54SMAR from GOSEMICON, in a ESOP-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply to the low-side gate driver, operating from 8V to 20V (absolute maximum 20V), with a 4.7uF bypass capacitor recommended. |
| 2 | HB | power_in | High-side bootstrap supply with an integrated 120V bootstrap diode; an external bootstrap capacitor (100nF recommended) is required, and an external boot diode cathode may be connected here instead, with HB-HS limited to 20V or less. |
| 3 | HO | output | High-side gate driver output, referenced to HS, to drive the high-side power MOSFET gate (pulse below -2V for less than 100ns tolerated). |
| 4 | HS | power_in | High-side source connection to the high-side MOSFET source, tolerating DC voltage from -1V to 100V (120V absolute maximum DC) and pulses down to -20V for less than 100ns. |
| 5 | HI | input | High-side logic input, TTL compatible with typical thresholds of 2.1V (high) and 1.1V (low), internally pulled down to VSS by about 220kΩ, and withstanding -10V to 20V. |
| 6 | LI | input | Low-side logic input, TTL compatible with typical thresholds of 2.1V (high) and 1.1V (low), internally pulled down to VSS by about 220kΩ, and withstanding -10V to 20V. |
| 7 | VSS | power_in | Negative supply terminal, serving as the reference ground for the low-side driver and logic. |
| 8 | LO | output | Low-side gate driver output, referenced to VSS, to drive the low-side power MOSFET gate (pulse below -2V for less than 100ns tolerated). |
| 9 | Thermal Pad | passive | Exposed thermal pad that must be grounded in the PCB layout. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GOSEMICON |
| Package | ESOP-8L |
| Category | Motor Driver ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | -0.3 | 20 | V | Over operating free-air temperature unless otherwise noted | 3 | |
| Logic Input | VLI, VHI | -10 | 20 | V | Over operating free-air temperature unless otherwise noted | 3 | |
| Voltage on Switching Node HS (DC) | VHS (DC) | -1 | 120 | V | Over operating free-air temperature unless otherwise noted | 3 | |
| Voltage on Switching Node HS (Pulse<100ns) | VHS (Pulse<100ns) | -20 | 120 | V | Over operating free-air temperature unless otherwise noted | 3 | |
| Voltage on HB | VHB | -0.3 | 120 | V | Over operating free-air temperature unless otherwise noted | 3 | |
| Operating junction temperature | TJ | -40 | 150 | °C | Over operating free-air temperature unless otherwise noted | 3 | |
| Storage temperature | TSTG | -65 | 150 | °C | Over operating free-air temperature unless otherwise noted | 3 | |
| ESD Human Body Model (HBM), all pins | VESD | -2000 | 2000 | V | ANSI-JEDEC-JS-001-2014 | 3 | |
| ESD Charged Device Model (CDM), all pins | VESD | -1000 | 1000 | V | ANSI-JEDEC-JS-002-2014 | 3 | |
| VDD Supply voltage range | VDD | 8 | 20 | V | Over operating free-air temperature range unless otherwise noted | 4 | |
| Input & Enable voltage range | VLI, HI | -10 | 20 | V | Over operating free-air temperature range unless otherwise noted | 4 | |
| Voltage on HS (DC) | VHS | -1 | 100 | V | Over operating free-air temperature range unless otherwise noted | 4 | |
| Voltage on HS (Pulse<100ns) | VHS | -18 | 100 | V | Over operating free-air temperature range unless otherwise noted | 4 | |
| Voltage slew rate on HS | 50 | V/ns | Over operating free-air temperature range unless otherwise noted | 4 | |||
| Operating junction temperature (recommended) | TJ | -40 | 150 | °C | Over operating free-air temperature range unless otherwise noted | 4 | |
| VDD quiescent current | IDD | 0.24 | 0.5 | mA | VDD=VHB=12V, TJ=-40°C~150°C; VLI=VHI=0 | 4 | |
| VDD operating current | IDDO | 2.2 | 5 | mA | VDD=VHB=12V, TJ=-40°C~150°C; f=500kHz, Cload=0 | 4 | |
| HB Quiescent current | IHB | 0.17 | 0.4 | mA | VDD=VHB=12V, TJ=-40°C~150°C; VLI=VHI=0 | 4 | |
| HB Operating current | IHBO | 2.1 | 4 | mA | VDD=VHB=12V, TJ=-40°C~150°C; f=500kHz, Cload=0 | 4 | |
| HB to VSS quiescent current | IHBS | 0 | 50 | uA | VDD=VHB=12V, TJ=-40°C~150°C | 4 | |
| HB rising threshold with respect to HS | VHBR | 5 | 6.8 | 8 | V | VDD=VHB=12V, TJ=-40°C~150°C | 5 |
| HB falling threshold with respect to HS | VHBF | 5 | 6.2 | 7 | V | VDD=VHB=12V, TJ=-40°C~150°C | 5 |
| Input rising threshold | VIH | 1.9 | 2.1 | 2.4 | V | VDD=VHB=12V, TJ=-40°C~150°C | 5 |
| Input falling threshold | VIT | 0.9 | 1.1 | 1.3 | V | VDD=VHB=12V, TJ=-40°C~150°C | 5 |
| Input pulldown resistance | RIN | 100 | 220 | 350 | kΩ | VDD=VHB=12V, TJ=-40°C~150°C | 5 |
| Low side low level output voltage | VLOL | 0.07 | 0.4 | V | VDD=VHB=12V, TJ=-40°C~150°C; ILO=100mA | 5 | |
| Low side high level output voltage | VLOH | 0.1 | 0.42 | V | VDD=VHB=12V, TJ=-40°C~150°C; ILO=-100mA, VLOH = VDD, VLO | 5 | |
| High side low level output voltage | VHOL | 0.07 | 0.4 | V | VDD=VHB=12V, TJ=-40°C~150°C; IHO=100mA | 5 | |
| High side high level output voltage | VHOH | 0.1 | 0.4 | V | VDD=VHB=12V, TJ=-40°C~150°C; IHO=-100mA, VHOH=VHB-VHO | 5 | |
| Low current forward voltage | VF | 0.5 | 0.8 | V | VDD=VHB=12V, TJ=-40°C~150°C; IVDD-HB=100uA | 5 | |
| High current forward voltage | VFI | 0.9 | 1 | V | VDD=VHB=12V, TJ=-40°C~150°C; IVDD-HB=100mA | 5 | |
| Dynamic resistance | RD | 0.5 | 1 | Ω | VDD=VHB=12V, TJ=-40°C~150°C | 5 | |
| Minimum input pulse that changes the output | TPW,min | 20 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 6 | ||
| VDD operating current (HB to VSS operating) | IHBSO | 1 | mA | VDD=VHB=12V, TJ=-40°C~150°C | 4 | ||
| VDD rising threshold | VDDR | 7 | V | VDD=VHB=12V, TJ=-40°C~150°C | 4 | ||
| VDD falling threshold | VDDF | 6.5 | V | VDD=VHB=12V, TJ=-40°C~150°C | 4 | ||
| VDD threshold hysteresis | VDDHYS | 0.5 | V | VDD=VHB=12V, TJ=-40°C~150°C | 4 | ||
| HB threshold hysteresis | VHBHYS | 0.6 | V | VDD=VHB=12V, TJ=-40°C~150°C | 5 | ||
| Input voltage Hysteresis | VIHYS | 1 | V | VDD=VHB=12V, TJ=-40°C~150°C | 5 | ||
| Output peak pullup current | ILSOURCE | 4 | A | VDD=VHB=12V, TJ=-40°C~150°C; VLO=0V | 5 | ||
| Output peak pulldown current | ILSINK | 4 | A | VDD=VHB=12V, TJ=-40°C~150°C; VLO=12V | 5 | ||
| Peak pullup current (high side) | IHSOURCE | 4 | A | VDD=VHB=12V, TJ=-40°C~150°C; VHO=0V | 5 | ||
| Peak pulldown current (high side) | IHSINK | 4 | A | VDD=VHB=12V, TJ=-40°C~150°C; VHO=12V | 5 | ||
| LO, HO Output rising time | TR | 7 | ns | VDD=VHB=12V, TJ=-40°C~150°C; CLoad=1.0nF | 5 | ||
| Output falling time | TF | 5 | ns | VDD=VHB=12V, TJ=-40°C~150°C; CLoad=1.0nF | 5 | ||
| VLI falling to VLO falling | TDLFF | 24 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 5 | ||
| VHI falling to VHO falling | TDHFF | 24 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 5 | ||
| VLI rising to VLO rising | TDLRR | 28 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 5 | ||
| VHI rising to VHO rising | TDHRR | 28 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 5 | ||
| From LO being ON to HO being OFF (delay matching) | TMON | 2 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 6 | ||
| From LO being OFF to HO being ON (delay matching) | TMOFF | 2 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 6 | ||
| Bootstrap diode turn off time | TBST | 50 | ns | VDD=VHB=12V, TJ=-40°C~150°C | 6 | ||
| Junction to ambient thermal resistance (eSOP-8L) | RθJA | 40 | °C/W | 4 | |||
| Junction to case thermal resistance (eSOP-8L) | RθJC | 48 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
GBI7A54SMAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8L (KiCad packages3D, STEP)
- 3D model files:
gbi7a54smar-etched.step/gbi7a54smar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gbi7a54smar.step/gbi7a54smar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GOSEMICON datasheet (19 pp, sha256
6083f7e7186336f9, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).