TPS5420D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT	passive	Boost capacitor for the high-side FET gate driver; connect a 0.01μF low ESR capacitor from BOOT pin to PH pin.
2	NC	unconnected	Not connected internally.
3	NC	unconnected	Not connected internally.
4	VSENSE	input	Feedback voltage for the regulator, connected to the output voltage divider.
5	ENA	input	On and off control: below 0.5V the device stops switching and above 1.3V it starts switching, with an internal 1.5MΩ pullup so it can be left floating.
6	GND	power_in	Ground.
7	VIN	power_in	Input supply voltage, bypassed to GND with a high quality low ESR ceramic capacitor placed within 1mm of the VIN and GND pins.
8	PH	output	Source of the high side power MOSFET, connected to the external inductor and diode.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage VIN to GND	VIN	-0.3		40	V		4
Input voltage ENA to GND	ENA	-0.3		7	V		4
Input voltage VSENSE to GND	VSENSE	-0.3		3	V		4
Output voltage BOOT to PH	BOOT-PH	-0.3		6	V		4
Output voltage PH to GND steady-state	PH	-0.6		40	V	Steady-state	4
PH leakage current				10	µA		4
Operating virtual junction temperature	TJ	-40		150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Input voltage range	VIN	5.5		36	V		4
Operating junction temperature	TJ	-40		125	°C		4
VIN quiescent current	IQ(VIN)		2	4.4	mA	Non-switching, VSENSE = 2V, PH pin open	5
VIN shutdown supply current	ISD(VIN)		15	50	µA	Shutdown, ENA = 0V	5
VIN UVLO rising threshold	VINUVLO(R)		5.3	5.5	V	VVIN rising	5
FB voltage at TJ = 25°C	VFB	1.202	1.221	1.239	V	TJ = 25°C	5
FB voltage over junction temperature	VFB	1.196	1.221	1.245	V	TJ = -40°C to 125°C	5
Switching frequency	fSW	400	500	600	kHz		5
Minimum ON pulse width	tON(min)		150	200	ns		5
Maximum duty cycle	DMAX		85	89	%	fSW = 500kHz	5
Internal slow-start time (0 to 100%)	tSS	6.6	8	10	ms		5
High-side peak current limit	IHS(OC)	3	4	5	A		5
Hiccup time before re-start		13	16	20	ms		5
High-side MOSFET on-resistance	RDSON(HS)		100	230	mΩ	VIN = 12V, VBOOT-SW = 4.5V	5
Thermal shutdown threshold	TJ(SD)		135	162	°C	Temperature rising	5
Junction-to-ambient thermal resistance (Custom Board)	RθJA		75		°C/W	Custom Board	4
Junction-to-ambient thermal resistance (JESD 51-7)	RθJA		106		°C/W	JESD 51-7	4
Junction-to-case (top) thermal resistance	RθJC(top)		54		°C/W		4
Junction-to-board thermal resistance	RθJB		55		°C/W		4
Junction-to-top characterization parameter	ψJT		15		°C/W		4
Junction-to-board characterization parameter	ψJB		56		°C/W		4

CAD (KiCad official)

Symbol: TPS5420D
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tps5420d-etched.step / tps5420d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps5420d.step / tps5420d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 cd667e69b40fa9c0, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS5420D

Verified TPS5420D

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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