component
SN74HCS72DR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSN74HCS72DR
Texas Instruments · Flip Flops · SOIC-14
SN74HCS72DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active-low clear input for channel 1; a low level resets output 1Q low, and the clear function is asynchronous and independent of the other inputs. |
| 2 | 1D | input | Data input for channel 1, sampled on the falling edge of 1CLK when 1PRE and 1CLR are inactive (high) and must meet the setup and hold times. |
| 3 | 1CLK | input | Clock input for channel 1, which is falling-edge triggered. |
| 4 | 1PRE | input | Active-low preset input for channel 1; a low level sets output 1Q high, and the preset function is asynchronous and independent of the other inputs. |
| 5 | 1Q | output | Output of channel 1. |
| 6 | 1Q | output | Inverted output of channel 1 (complement of 1Q). |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 2Q | output | Inverted output of channel 2 (complement of 2Q). |
| 9 | 2Q | output | Output of channel 2. |
| 10 | 2PRE | input | Active-low preset input for channel 2; a low level sets output 2Q high, and the preset function is asynchronous and independent of the other inputs. |
| 11 | 2CLK | input | Clock input for channel 2, which is falling-edge triggered. |
| 12 | 2D | input | Data input for channel 2, sampled on the falling edge of 2CLK when 2PRE and 2CLR are inactive (high) and must meet the setup and hold times. |
| 13 | 2CLR | input | Active-low clear input for channel 2; a low level resets output 2Q low, and the clear function is asynchronous and independent of the other inputs. |
| 14 | VCC | power_in | Positive supply pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC + 0.5 V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC + 0.5 V | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | Tj | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 133.6 | °C/W | D (SOIC) 14-pin package | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 89 | °C/W | D (SOIC) 14-pin package | 4 | ||
| Junction-to-board thermal resistance | RθJB | 89.5 | °C/W | D (SOIC) 14-pin package | 4 | ||
| Junction-to-top characterization parameter | ΨJT | 45.5 | °C/W | D (SOIC) 14-pin package | 4 | ||
| Junction-to-board characterization parameter | ΨJB | 89.1 | °C/W | D (SOIC) 14-pin package | 4 | ||
| Positive switching threshold | VT+ | 0.7 | 1.5 | V | VCC = 2 V | 5 | |
| Positive switching threshold | VT+ | 1.7 | 3.15 | V | VCC = 4.5 V | 5 | |
| Positive switching threshold | VT+ | 2.1 | 4.2 | V | VCC = 6 V | 5 | |
| Negative switching threshold | VT- | 0.3 | 1 | V | VCC = 2 V | 5 | |
| Negative switching threshold | VT- | 0.9 | 2.2 | V | VCC = 4.5 V | 5 | |
| Negative switching threshold | VT- | 1.2 | 3 | V | VCC = 6 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | 1 | V | VCC = 2 V; tt = tr or tf, whichever is larger | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | 1.4 | V | VCC = 4.5 V; tt = tr or tf, whichever is larger | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | 1.6 | V | VCC = 6 V; tt = tr or tf, whichever is larger | 5 | |
| High-level output voltage | VOH | 4 | 4.3 | V | VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V | 5 | |
| High-level output voltage | VOH | 5.4 | 5.75 | V | VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V | 5 | |
| Low-level output voltage | VOL | 0.002 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC = 2 V to 6 V | 5 | |
| Low-level output voltage | VOL | 0.18 | 0.3 | V | VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.22 | 0.33 | V | VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V | 5 | |
| Input leakage current | II | -1000 | 100 | 1000 | nA | VI = VCC or 0; VCC = 6 V | 5 |
| Supply current | ICC | 0.1 | 2 | µA | VI = VCC or 0; IO = 0; VCC = 6 V | 5 | |
| Max switching frequency | fmax | 20 | 31 | MHz | CL = 50 pF; VCC = 2 V | 5 | |
| Max switching frequency | fmax | 64 | 95 | MHz | CL = 50 pF; VCC = 4.5 V | 5 | |
| Max switching frequency | fmax | 74 | 105 | MHz | CL = 50 pF; VCC = 6 V | 5 | |
| Propagation delay (PRE or CLR to Q or Q) | tpd | 19 | 42 | ns | CL = 50 pF; VCC = 2 V | 5 | |
| Propagation delay (PRE or CLR to Q or Q) | tpd | 8 | 19 | ns | CL = 50 pF; VCC = 4.5 V | 5 | |
| Propagation delay (PRE or CLR to Q or Q) | tpd | 7 | 15 | ns | CL = 50 pF; VCC = 6 V | 5 | |
| Propagation delay (CLK to Q or Q) | tpd | 19 | 42 | ns | CL = 50 pF; VCC = 2 V | 5 | |
| Propagation delay (CLK to Q or Q) | tpd | 8 | 19 | ns | CL = 50 pF; VCC = 4.5 V | 5 | |
| Propagation delay (CLK to Q or Q) | tpd | 7 | 15 | ns | CL = 50 pF; VCC = 6 V | 5 | |
| Transition time (Q or Q) | tt | 9 | 16 | ns | CL = 50 pF; VCC = 2 V | 5 | |
| Transition time (Q or Q) | tt | 5 | 9 | ns | CL = 50 pF; VCC = 4.5 V | 5 | |
| Transition time (Q or Q) | tt | 4 | 8 | ns | CL = 50 pF; VCC = 6 V | 5 | |
| Clock frequency | fclock | 20 | MHz | CL = 50 pF; VCC = 2 V | 6 | ||
| Clock frequency | fclock | 64 | MHz | CL = 50 pF; VCC = 4.5 V | 6 | ||
| Clock frequency | fclock | 74 | MHz | CL = 50 pF; VCC = 6 V | 6 | ||
| Hold time, data after CLK falling | th | 5 | ns | VCC = 2 V | 6 | ||
| Hold time, data after CLK falling | th | 3 | ns | VCC = 4.5 V | 6 | ||
| Hold time, data after CLK falling | th | 2 | ns | VCC = 6 V | 6 | ||
| Setup time, PRE or CLR inactive | tsu | 7 | ns | VCC = 2 V | 6 | ||
| Setup time, PRE or CLR inactive | tsu | 0 | ns | VCC = 4.5 V | 6 | ||
| Input capacitance | Ci | 5 | pF | VCC = 2 V to 6 V | 5 | ||
| Power dissipation capacitance | Cpd | 10 | pF | Per gate; no load; VCC = 2 V to 6 V | 5 |
CAD (KiCad official)
- Symbol:
SN74HCS72DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hcs72dr-etched.step/sn74hcs72dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hcs72dr.step/sn74hcs72dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
086577e766a4cae8, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).