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Contents

README

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IR2110-MNS

Minos · Gate Drivers · DIP-14

IR2110-MNS from Minos, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LO output Low-side gate driver output, which operates between 0 V and VCC under the recommended conditions and has a 4.0 A typical pulse source/sink current (PW ≤ 10 µs).
2 COM power_in Low-side return, the reference for VCC and LO, with COM-to-VSS voltage withstand limited to ±5.0 V.
3 VCC power_in Low-side supply, recommended 10 V to 20 V (absolute maximum −0.3 V to 25.0 V), with the low-side UVLO thresholds at 8.9 V rising and 8.2 V falling.
4 NC unconnected Not connected.
5 VS power_in High-side floating supply return, recommended −9 V to 700 V, with absolute maximum VB − 25.0 V to VB + 0.3 V.
6 VB power_in High-side floating supply, recommended VS + 10 V to VS + 20 V (absolute maximum −0.3 V to 725.0 V).
7 HO output High-side gate driver output referenced to VS, with output voltage between VS and VB under the recommended conditions.
8 NC unconnected Not connected.
9 VDD power_in Logic supply, recommended VSS + 3 V to VSS + 20 V.
10 HIN input High-side logic input, in phase with HO, with input voltage between VSS and VDD and compatibility with 3.3 V, 5 V and 15 V logic.
11 SD input Shutdown logic input for the high- and low-side outputs, with input voltage between VSS and VDD.
12 LIN input Low-side logic input, in phase with LO, with input voltage between VSS and VDD.
13 VSS power_in Logic ground, recommended −5 V to +5 V.
14 NC unconnected Not connected.

Key specifications

Parameter Value
Manufacturer Minos
Package DIP-14
Category Motor Driver ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-side floating supply voltage VB VB -0.3 725 V 5
Low-side supply voltage VCC VCC -0.3 25 V 5
Low-side floating output voltage VLO (min only; max is VCC+0.3) VLO -0.3 V 5
Logic supply voltage VDD (min only; max is VSS+25.0) VDD -0.3 V 5
Logic supply bias voltage VSS VSS -5 5 V 5
Allowed offset voltage slew rate dVS/dt dVS/dt 50 V/ns 5
Power dissipation PD (14-PDIP) PD 1.6 W 14-PDIP; notes 1,2,3 5
Maximum junction temperature TJ TJ 150 ℃ 5
Storage temperature TSTG TSTG -55 150 ℃ 5
Thermal resistance, junction to ambient (14-PDIP) 8JA 75 ℃/W 14-PDIP 5
High-side floating supply offset voltage VS VS -9 700 V 5
Low-side supply voltage VCC VCC 10 20 V 5
Low-side output voltage VLO (max is VCC) VLO 0 V 5
Logic supply bias voltage VSS VSS -5 5 V 5
Ambient temperature TA TA -40 125 C 5
VCC quiescent supply current IQCC 40 80 μA VIN = 0 V or VDD 6
VDD quiescent supply current IQDD 10 μA VIN = 0 V or VDD 6
VBS quiescent supply current IQBS 60 130 μA VIN = 0 V or VDD 6
VCC undervoltage positive-going threshold VCCUV+ 8 8.9 9.8 V VIN = 0 V, VCC = 扫描 (sweep) 6
VCC undervoltage negative-going threshold VCCUV− 7.4 8.2 9 V VIN = 0 V, VCC = 扫描 (sweep) 6
VBS undervoltage positive-going threshold VBSUV+ 8 8.9 9.8 V VIN = 0 V, VBS = 扫描 (sweep) 6
VBS undervoltage negative-going threshold VBSUV− 7.4 8.2 9 V VIN = 0 V, VBS = 扫描 (sweep) 6
Offset supply leakage current ILK 50 μA VB = VS = 700 V 6
Logic '1' input threshold voltage VIH 2.4 V VDD = 3 V 6
Logic '1' input threshold voltage VIH 9.5 V VDD = 15 V 6
Logic '0' input threshold voltage VIL 0.8 V VDD = 3 V 6
Logic '0' input threshold voltage VIL 6 V VDD = 15 V 6
Logic input high bias current IIN+ 20 40 μA VIN = VDD 6
Logic input low bias current IIN− 3 μA VIN = 0 V 6
Logic input pull-down resistance RIN 375 750 KΩ 6
High-level output voltage (VBIAS − VO) VOH 1.5 V No load (IO = 0 A) 6
Low-level output voltage VOL 200 mV No load (IO = 0 A) 6
Output high-level short-circuit pulsed current IO+ IO+ 3 4 A VO = 0 V, PW ≤ 10 μs; note 4 6
Output low-level short-circuit pulsed current IO− IO− 3 4 A VO = 15 V, PW ≤ 10 μs; note 4 6
VSS/COM voltage withstand Vss-COM/COM-Vss -5 5 V 6
Allowed negative VS voltage when HIN signal propagates to HO −VS -9.8 -7 V 6
Turn-on propagation delay ton ton 130 200 ns VS = 0 V 7
Turn-off propagation delay toff toff 130 200 ns VS = 700 V 7
Shutdown propagation delay tsd tsd 130 200 ns VS = 700 V; note 5 7
Turn-on rise time tr tr 25 35 ns 7
Turn-off fall time tf tf 17 25 ns 7
Delay matching, HO and LO on/off MT MT 10 7

CAD (KiCad official)

  • Symbol: IR2110-MNS
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: ir2110-mns-etched.step / ir2110-mns-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ir2110-mns.step / ir2110-mns.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Minos datasheet (16 pp, sha256 9eae9aac76f56461, retrieved 2026-10-15, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF