component
MP6539GF-Z
Public Made by Adomby adom
Monolithic Power Systems Gate Drivers, TSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMP6539GF-Z
Monolithic Power Systems · Gate Drivers · TSSOP-28-EP
MP6539GF-Z from Monolithic Power Systems, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LSC | input | Phase C low-side input pin, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 2 | LSB | input | Phase B low-side input pin, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 3 | LSA | input | Phase A low-side input pin, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 4 | HSC | input | Phase C high-side input pin, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 5 | HSB | input | Phase B high-side input pin, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 6 | HSA | input | Phase A high-side input pin, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 7 | nFAULT | output | Open-drain fault indication output that is logic low in a fault condition (VOL 0.1V at 5mA). |
| 8 | nSLEEP | input | Sleep mode input with internal pulldown (about 450kΩ); logic low enters low-power sleep mode, high enables the device. |
| 9 | OCREF | input | Over-current protection reference input, recommended 0.125V to 2.4V. |
| 10 | DT | passive | Dead time setting pin; a resistor to GND sets tDEAD = 0.044*R(kΩ)+0.1 µs, DT tied to GND gives minimum dead time, open gives 6µs. |
| 11 | GND | power_in | Ground. |
| 12 | VIN | power_in | Input supply voltage, 8V to 100V recommended operating range. |
| 13 | CSO | output | Current sense output and OCP off time adjust; requires at least 1nF to ground. |
| 14 | LDO | power_out | Gate drive LDO output (12V typ) and base drive for external NPN transistor, supports about 5mA internally. |
| 15 | VREG | power_in | Gate driver supply voltage, 8.5V to 14V recommended operating range. |
| 16 | BSTA | passive | Bootstrap output phase A, rated -0.3V to 120V. |
| 17 | SHA | passive | High-side source connection phase A, rated -5V to 110V. |
| 18 | GHA | output | High-side gate drive phase A. |
| 19 | GLA | output | Low-side gate drive phase A, rated -0.3V to 14.5V. |
| 20 | BSTB | passive | Bootstrap output phase B, rated -0.3V to 120V. |
| 21 | SHB | passive | High-side source connection phase B, rated -5V to 110V. |
| 22 | GHB | output | High-side gate drive phase B. |
| 23 | GLB | output | Low-side gate drive phase B, rated -0.3V to 14.5V. |
| 24 | BSTC | passive | Bootstrap output phase C, rated -0.3V to 120V. |
| 25 | SHC | passive | High-side source connection phase C, rated -5V to 110V. |
| 26 | GHC | output | High-side gate drive phase C. |
| 27 | GLC | output | Low-side gate drive phase C, rated -0.3V to 14.5V. |
| 28 | LSS | input | Low-side source connection (current sense input, amplified by 20 to CSO), rated -0.3V to 4V. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | TSSOP-28-EP |
| Category | Motor Driver ICs |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage | VIN | 8 | 100 | V | 4 | ||
| LDO output voltage | VLDO | 10.8 | 12 | 13.2 | V | ILDO ≤ 5mA, VIN > 15V | 4 |
| Gate driver supply voltage | VREG | 8.5 | 14 | V | 4 | ||
| Logic input current high | IIN(H) | -2.4 | 2.4 | µA | VIH = 0.8V | 4 | |
| Logic input current low | IIN(L) | -14 | 14 | µA | VIL = 5V | 4 | |
| VREG UVLO rising threshold | VREG_RUVLO | 6.5 | 7.5 | 8.5 | V | 4 | |
| VREG UVLO falling threshold | VREG_FUVLO | 6 | 6.8 | 7.6 | V | 4 | |
| VIN UVLO rising threshold | VVIN_RUVLO | 3.6 | 4 | 4.4 | V | 4 | |
| VIN UVLO falling threshold | VVIN_FUVLO | 3.4 | 3.8 | 4.3 | V | 4 | |
| OCREF threshold | VOC | 0.8 | 1 | 1.2 | V | VOC = 1V | 4 |
| OCREF threshold | VOC | 2.18 | 2.4 | 2.62 | V | VOC = 2.4V | 4 |
| HS gate drive pull-down resistance | RHS-DN | 0.6 | 4.5 | Ω | VDS = 1V | 4 | |
| LS gate drive pull-down resistance | RLS-DN | 0.6 | 4.5 | Ω | VDS = 1V | 4 | |
| Quiescent current | IQ | 0.7 | mA | nSLEEP = 1, not switching | 4 | ||
| Sleep current | ISLEEP | 1 | µA | nSLEEP = 0 | 4 | ||
| Input logic low threshold | VIL | 0.8 | V | 4 | |||
| Input logic high threshold | VIH | 2 | V | 4 | |||
| nSLEEP pull-down resistance | RSLEEP-PD | 450 | kΩ | 4 | |||
| Internal pull down resistance | RPD | 450 | kΩ | 4 | |||
| Fault output low voltage | VOL | 0.1 | V | IO = 5mA | 4 | ||
| Fault output high leakage current | IOH | 1 | µA | VO = 3.3V | 4 | ||
| VREG UVLO hysteresis | VREG_HYS | 610 | mV | 4 | |||
| VIN UVLO hysteresis | VVIN_HYS | 100 | mV | 4 | |||
| VBST UVLO threshold | VBST_UVLO | 4 | V | Voltage between SHx and BSTx | 4 | ||
| OCP deglitch time | tOC | 2.7 | µs | 4 | |||
| Sleep wake-up time | tSLEEP | 2 | ms | 4 | |||
| Thermal shutdown | TTSD | 175 | °C | Guaranteed by design | 4 | ||
| Thermal shutdown hysteresis | TTSD_HYS | 20 | °C | Guaranteed by design | 4 | ||
| Bootstrap diode forward voltage | VFBOOT | 1.2 | V | ID = 10mA | 4 | ||
| Bootstrap diode forward voltage | VFBOOT | 2.3 | V | ID = 50mA | 4 | ||
| Maximum source current | DSO | 0.8 | A | Guaranteed by design | 4 | ||
| Maximum sink current | DSI | 1 | A | Guaranteed by design | 4 | ||
| Gate drive pull-up resistance | RUP | 7 | Ω | VDS = 1V | 4 | ||
| LS automatic turn-on time | tLS | 4.6 | µs | 4 | |||
| Dead time | tDEAD | 560 | ns | RDT = 10kΩ | 4 | ||
| Dead time | tDEAD | 4.5 | µs | RDT = 100kΩ | 4 | ||
| Dead time | tDEAD | 77 | ns | DT tied to GND | 4 | ||
| Input voltage | VIN | -0.3 | 110 | V | 3 | ||
| Input voltage VREG, GLA/B/C | VREG | -0.3 | 14.5 | V | 3 | ||
| LDO voltage | LDO | -0.3 | 14.5 | V | 3 | ||
| BSTA/B/C voltage | BST | -0.3 | 120 | V | 3 | ||
| LSS voltage | LSS | -0.3 | 4 | V | 3 | ||
| LSS voltage transient | LSS | -1 | 4 | V | transient, 2µs | 3 | |
| SHA/B/C voltage | SH | -5 | 110 | V | 3 | ||
| SHA/B/C voltage transient | SH | -8 | 110 | V | transient, 2µs | 3 | |
| All other pins to GND | -0.3 | 6.5 | V | 3 | |||
| Continuous power dissipation TSSOP-28 EP | PD | 3.9 | W | TA = +25°C | 3 | ||
| Storage temperature | TSTG | -55 | 150 | °C | 3 | ||
| Junction temperature | TJ | 150 | °C | 3 | |||
| Lead temperature (solder) | 260 | °C | 3 | ||||
| Input voltage (recommended) | VIN | 8 | 100 | V | 3 | ||
| VREG voltage (recommended) | VREG | 8.5 | 14 | V | 3 | ||
| OCREF voltage | VOC | 0.125 | 2.4 | V | 3 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| Thermal resistance junction-ambient TSSOP-28 EP | θJA | 32 | °C/W | JESD51-7, 4-layer PCB | 3 | ||
| Thermal resistance junction-case TSSOP-28 EP | θJC | 6 | °C/W | JESD51-7, 4-layer PCB | 3 |
CAD (KiCad official)
- Symbol:
MP6539GF-Z - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
mp6539gf-z-etched.step/mp6539gf-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp6539gf-z.step/mp6539gf-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (15 pp, sha256
409284a676a5ee03, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).