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ATSAME70N19B-AN

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Microchip Tech Pre-ordered MCUs, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatsame70n19b-anfactory-2.0.0extractor-text

Verified ATSAME70N19B-AN

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAME70N19B-AN · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 1943-page datasheet
  • ✓distributor: lcsc C612614, digikey ATSAME70N19B-AN-ND, mouser 556-ATSAME70N19B-AN
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ps0qdy5g/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.1913)
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atsame70n19b-an.kicad_sym✓ atsame70n19b-an.kicad_mod✓ atsame70n19b-an.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

ATSAME70N19B-AN

Microchip Tech · Pre-ordered MCUs · LQFP-100(14x14)

ATSAME70N19B-AN from Microchip Tech, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD0 bidirectional VDDIO GPIO_AD line PD0 with extra function DAC1 and peripheral options GTXCK, PWMC1_PWML0, SPI1_NPCS1, DCD0; resets as PIO input with pull-up and Schmitt trigger.
2 PD31 bidirectional VDDIO GPIO_AD line PD31 with peripheral options QIO3, UTXD3, PCK2 and ISI_D11; resets as PIO input with pull-up and Schmitt trigger.
3 GND power_in Ground for the voltage regulator, core chip and peripheral I/O lines.
4 VDDOUT power_out Voltage regulator output.
5 VDDIN power_in Voltage regulator input that also supplies the AFE, DAC and analog comparator; must be at the same level as VDDIO and not below VDDCORE.
6 VREFN input Negative reference voltage input for the analog front-end (listed with GND power rail).
7 GND power_in Ground for the voltage regulator, core chip and peripheral I/O lines.
8 GND power_in Ground for the voltage regulator, core chip and peripheral I/O lines.
9 VREFP input Positive reference voltage input for the AFE and DAC; must rise simultaneously with VDDIO and VDDIN.
10 GND power_in Ground for the voltage regulator, core chip and peripheral I/O lines.
11 PB1 bidirectional VDDIO GPIO line PB1 with AFE1_AD0/RTCOUT1 and peripheral options PWMC0_PWMH1, GTSUCOMP, TXD0, TK.
12 PB0 bidirectional VDDIO GPIO line PB0 with AFE0_AD10/RTCOUT0 and peripheral options PWMC0_PWMH0, RXD0, TF.
13 PA20 bidirectional VDDIO GPIO_AD line PA20 with AFE0_AD9/WKUP10 and peripheral options PWMC0_PWML1, A16, I2SC1_CK.
14 PA19 bidirectional VDDIO GPIO_AD line PA19 with AFE0_AD8/WKUP9 and peripheral options PWMC0_PWML0, A15, I2SC1_MCK.
15 PA18 bidirectional VDDIO GPIO_AD line PA18 with AFE0_AD7 and peripheral options PWMC1_PWMEXTRG1, PCK2, A14.
16 PA17 bidirectional VDDIO GPIO_AD line PA17 with AFE0_AD6 and peripheral options QIO2, PCK1, PWMC0_PWMH3.
17 PB2 bidirectional VDDIO GPIO line PB2 with AFE0_AD5 and peripheral options CANTX0, CTS0, SPI0_NPCS0.
18 VDDCORE power_in Core, embedded memory and peripheral supply; must not exceed VDDIN/VDDIO.
19 VDDIO power_in Supply for peripheral I/O lines, backup part, 32 kHz oscillator and oscillator pads; must equal VDDIN (3.0V to 3.6V for USB).
20 PB3 bidirectional VDDIO GPIO_AD line PB3 with AFE0_AD2/WKUP12 and peripheral options CANRX0, PCK2, RTS0, ISI_D2.
21 PA21 bidirectional VDDIO GPIO_AD line PA21 with AFE0_AD1/PIODCEN2 and peripheral options RXD1, PCK1, PWMC1_PWMFI0.
22 VDDCORE power_in Core, embedded memory and peripheral supply; must not exceed VDDIN/VDDIO.
23 PD30 bidirectional VDDIO GPIO_AD line PD30 with AFE0_AD0 and peripheral options UTXD3, ISI_D10.
24 PA7 bidirectional VDDIO CLOCK line PA7 used as XIN32 32.768 kHz oscillator input, with alternate PWMC0_PWMH3; resets to PIO, HiZ.
25 PA8 bidirectional VDDIO CLOCK line PA8 used as XOUT32 32.768 kHz oscillator output, with alternates PWMC1_PWMH3 and AFE0_ADTRG; resets to PIO, HiZ.
26 PA22 bidirectional VDDIO GPIO_AD line PA22 with PIODCCLK and peripheral options RK, PWMC0_PWMEXTRG1, NCS2.
27 PA13 bidirectional VDDIO GPIO_AD line PA13 with PIODC7 and peripheral options QIO0, PWMC0_PWMH2, PWMC1_PWML1.
28 VDDIO power_in Supply for peripheral I/O lines, backup part, 32 kHz oscillator and oscillator pads; must equal VDDIN (3.0V to 3.6V for USB).
29 GND power_in Ground for the voltage regulator, core chip and peripheral I/O lines.
30 PA16 bidirectional VDDIO GPIO_AD line PA16 with peripheral options D15, TIOB1, PWMC0_PWML2, I2SC0_DI.
31 PA23 bidirectional VDDIO GPIO_AD line PA23 with peripheral options SCK1, PWMC0_PWMH0, A19, PWMC1_PWML2.
32 PD27 bidirectional VDDIO GPIO_AD line PD27 with peripheral options PWMC0_PWML3, SPI0_NPCS3, TWD2, ISI_D8.
33 PA15 bidirectional VDDIO GPIO_AD line PA15 with peripheral options D14, TIOA1, PWMC0_PWML3, I2SC0_WS.
34 PA14 bidirectional VDDIO GPIO_CLK line PA14 with WKUP8/PIODCEN1 and peripheral options QSCK, PWMC0_PWMH3, PWMC1_PWMH1.
35 PD25 bidirectional VDDIO GPIO_AD line PD25 with peripheral options PWMC0_PWML1, SPI0_NPCS1, URXD2, ISI_VSYNC.
36 PD26 bidirectional VDDIO GPIO line PD26 with peripheral options PWMC0_PWML2, TD, UTXD2, UTXD1.
37 PD24 bidirectional VDDIO GPIO_AD line PD24 with peripheral options PWMC0_PWML0, RF, TCLK11, ISI_HSYNC.
38 PA24 bidirectional VDDIO GPIO_AD line PA24 with peripheral options RTS1, PWMC0_PWMH1, A20, ISI_PCK.
39 VDDCORE power_in Core, embedded memory and peripheral supply; must not exceed VDDIN/VDDIO.
40 PA25 bidirectional VDDIO GPIO_AD line PA25 with peripheral options CTS1, PWMC0_PWMH2, A23, MCCK.
41 PD22 bidirectional VDDIO GPIO_AD line PD22 with peripheral options PWMC0_PWMH2, SPI0_SPCK, TIOB11, ISI_D0.
42 PA26 bidirectional VDDIO GPIO line PA26 with peripheral options DCD1, TIOA2, MCDA2, PWMC1_PWMFI1.
43 PD21 bidirectional VDDIO GPIO_AD line PD21 with peripheral options PWMC0_PWMH1, SPI0_MOSI, TIOA11, ISI_D1.
44 PA11 bidirectional VDDIO GPIO_AD line PA11 with WKUP7/PIODC5 and peripheral options QCS, PWMC0_PWMH0, PWMC1_PWML0.
45 PD20 bidirectional VDDIO GPIO line PD20 with peripheral options PWMC0_PWMH0, SPI0_MISO, GTSUCOMP.
46 PA10 bidirectional VDDIO GPIO_AD line PA10 with PIODC4 and peripheral options UTXD0, PWMC0_PWMEXTRG0, RD.
47 PD19 bidirectional VDDIO GPIO_AD line PD19 with peripheral options NCS3, CTS2, UTXD4.
48 PA12 bidirectional VDDIO GPIO_AD line PA12 with PIODC6 and peripheral options QIO1, PWMC0_PWMH1, PWMC1_PWMH0.
49 PD18 bidirectional VDDIO GPIO_AD line PD18 with peripheral options NCS1, RTS2, URXD4.
50 PA27 bidirectional VDDIO GPIO_AD line PA27 with peripheral options DTR1, TIOB2, MCDA3, ISI_D7.
51 PD28 bidirectional VDDIO GPIO_AD line PD28 with WKUP5 and peripheral options URXD3, CANRX1, TWCK2, ISI_D9.
52 PA5 bidirectional VDDIO GPIO_AD line PA5 with WKUP4/PIODC2 and peripheral options PWMC1_PWML3, ISI_D4, URXD1.
53 PD17 bidirectional VDDIO GPIO_AD line PD17 with peripheral options GTXER, SCK2.
54 PA9 bidirectional VDDIO GPIO_AD line PA9 with WKUP6/PIODC3 and peripheral options URXD0, ISI_D3, PWMC0_PWMFI0.
55 PA4 bidirectional VDDIO GPIO line PA4 with WKUP3/PIODC1 and peripheral options TWCK0, TCLK0, UTXD1.
56 PD16 bidirectional VDDIO GPIO_AD line PD16 with peripheral options GTX3, TXD2.
57 PB6 bidirectional VDDIO GPIO line PB6 used by default as SWDIO/TMS debug input; configurable via CCFG_SYSIO.
58 NRST input Microcontroller reset input (active low) on VDDIO with internal pull-up.
59 PD14 bidirectional VDDIO GPIO_AD line PD14 with peripheral option GRXCK.
60 TST input Test select input with internal pull-down of about 15 kΩ; may be left unconnected in normal operation.
61 PB12 bidirectional VDDIO GPIO line PB12 used as ERASE input at reset (pull-down), with PWMC0_PWML1, GTSUCOMP, PCK0 options.
62 PD13 bidirectional VDDIO GPIO_AD line PD13 with peripheral option GCOL.
63 PB7 bidirectional VDDIO GPIO line PB7 used by default as SWCLK/TCK debug input; configurable via CCFG_SYSIO.
64 PA3 bidirectional VDDIO GPIO_AD line PA3 with PIODC0 and peripheral options TWD0, LONCOL1, PCK2.
65 PD12 bidirectional VDDIO GPIO_AD line PD12 with peripheral options GRX3, CANTX1, SPI0_NPCS2, ISI_D6.
66 PA2 bidirectional VDDIO GPIO line PA2 with WKUP2 and peripheral options PWMC0_PWMH1, DATRG.
67 GND power_in Ground for the voltage regulator, core chip and peripheral I/O lines.
68 VDDIO power_in Supply for peripheral I/O lines, backup part, 32 kHz oscillator and oscillator pads; must equal VDDIN (3.0V to 3.6V for USB).
69 PD11 bidirectional VDDIO GPIO_AD line PD11 with peripheral options GRX2, PWMC0_PWMH0, GTSUCOMP, ISI_D5.
70 PA1 bidirectional VDDIO GPIO_AD line PA1 with WKUP1 and peripheral options PWMC0_PWML0, TIOB0, A18, I2SC0_CK.
71 PD10 bidirectional VDDIO GPIO_MLB line PD10 with peripheral options GCRS, PWMC0_PWML0, TD, MLBSIG; resets as PIO input with pull-down.
72 PA0 bidirectional VDDIO GPIO_AD line PA0 with WKUP0 and peripheral options PWMC0_PWMH0, TIOA0, A17, I2SC0_MCK.
73 JTAGSEL input JTAG boundary-scan select input (high selects JTAG) with internal pull-down; SW-DP is selected when low.
74 PB4 bidirectional VDDIO GPIO_MLB line PB4 used as TDI at reset, with peripheral options TWD1, PWMC0_PWMH2, MLBCLK, TXD1.
75 PD15 bidirectional VDDIO GPIO_AD line PD15 with peripheral options GTX2, RXD2, NWR1/NBS1.
76 VDDCORE power_in Core, embedded memory and peripheral supply; must not exceed VDDIN/VDDIO.
77 PB5 bidirectional VDDIO GPIO_MLB line PB5 used as TDO/TRACESWO/WKUP13, with peripheral options TWCK1, PWMC0_PWML0, MLBDAT, TD; reset state O, PU.
78 PD9 bidirectional VDDIO GPIO_CLK line PD9 with peripheral options GMDIO, PWMC0_PWMFI2, AFE1_ADTRG.
79 PA28 bidirectional VDDIO GPIO line PA28 with peripheral options DSR1, TCLK1, MCCDA, PWMC1_PWMFI2.
80 PD8 bidirectional VDDIO GPIO_CLK line PD8 with peripheral options GMDC, PWMC0_PWMFI1, TRACECLK.
81 VDDIO power_in Supply for peripheral I/O lines, backup part, 32 kHz oscillator and oscillator pads; must equal VDDIN (3.0V to 3.6V for USB).
82 PA30 bidirectional VDDIO GPIO line PA30 with WKUP11 and peripheral options PWMC0_PWML2, PWMC1_PWMEXTRG0, MCDA0, I2SC0_DO.
83 PA31 bidirectional VDDIO GPIO_AD line PA31 with peripheral options SPI0_NPCS1, PCK2, MCDA1, PWMC1_PWMH2.
84 PD7 bidirectional VDDIO GPIO_CLK line PD7 with peripheral options GRXER, PWMC1_PWMH3, TRACED3, RI2.
85 PD6 bidirectional VDDIO GPIO_CLK line PD6 with peripheral options GRX1, PWMC1_PWML3, TRACED2, DSR2.
86 VDDPLL power_in Supply for PLLA and the fast RC oscillator; noise sensitive.
87 PD5 bidirectional VDDIO GPIO_CLK line PD5 with peripheral options GRX0, PWMC1_PWMH2, TRACED1, DTR2.
88 PD4 bidirectional VDDIO GPIO_CLK line PD4 with peripheral options GRXDV, PWMC1_PWML2, TRACED0, DCD2.
89 PD3 bidirectional VDDIO GPIO line PD3 with peripheral options GTX1, PWMC1_PWMH1, UTXD4, RI0.
90 VDDPLLUSB power_in Supply for the UTMI PLL and 3 to 20 MHz oscillator; noise sensitive, 3.0V to 3.6V for USB operation.
91 PD2 bidirectional VDDIO GPIO line PD2 with peripheral options GTX0, PWMC1_PWML1, SPI1_NPCS3, DSR0.
92 PD1 bidirectional VDDIO GPIO line PD1 with peripheral options GTXEN, PWMC1_PWMH0, SPI1_NPCS2, DTR0.
93 VDDUTMII power_in USB transceiver interface supply; must be connected to VDDIO (3.0V to 3.6V for USB).
94 HSDM bidirectional USB high-speed data minus (D-) line.
95 HSDP bidirectional USB high-speed data plus (D+) line.
96 VDDUTMIC power_in USB transceiver core supply; must always be connected even if USB is unused.
97 VBG input Bias/band-gap pin (VBG), listed as input with no power rail.
98 PB8 bidirectional VDDIOP CLOCK line PB8 used as XOUT main crystal oscillator output; resets to PIO, HiZ.
99 PB9 bidirectional VDDIOP CLOCK line PB9 used as XIN main crystal oscillator input; resets to PIO, HiZ.
100 PB13 bidirectional VDDIO GPIO_AD line PB13 with DAC0 output and peripheral options PWMC0_PWML2, PCK0, SCK0.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: ATSAME70N19B-AN
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: atsame70n19b-an-etched.step / atsame70n19b-an-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsame70n19b-an.step / atsame70n19b-an.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1943 pp, sha256 94ed9d6997caca1c, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF