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CD4070B Quad XOR Gate

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Quad 2-input exclusive-OR (XOR) gate in the 4000B CMOS family, 3 V to 18 V.

logicxorexclusive-or4000-seriestisoic-14
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CD4070B

Texas Instruments · Logic Gate · SOIC-14

The CD4070B contains four independent 2-input exclusive-OR (XOR) gates in the 4000B CMOS family. Each output is high when the inputs differ, useful for parity generation and checking, controlled inversion, and single-bit comparison. It runs from 3 V to 18 V.

Pinout

Pin Name Type Function
1 A input Gate 1 input A. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 2 (B) to produce J = A XOR B on pin 3.
2 B input Gate 1 input B. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 1 (A) to produce J = A XOR B on pin 3.
3 J output Gate 1 output, J = A XOR B (pins 1 XOR 2). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical).
4 K output Gate 2 output, K = C XOR D (pins 5 XOR 6). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical).
5 C input Gate 2 input C. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 6 (D) to produce K = C XOR D on pin 4.
6 D input Gate 2 input D. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 5 (C) to produce K = C XOR D on pin 4.
7 VSS power_in Negative supply / ground reference (0 V). All input/output voltages are referenced to VSS.
8 E input Gate 3 input E. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 9 (F) to produce L = E XOR F on pin 10.
9 F input Gate 3 input F. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 8 (E) to produce L = E XOR F on pin 10.
10 L output Gate 3 output, L = E XOR F (pins 8 XOR 9). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical).
11 M output Gate 4 output, M = G XOR H (pins 12 XOR 13). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical).
12 G input Gate 4 input G. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 13 (H) to produce M = G XOR H on pin 11.
13 H input Gate 4 input H. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 12 (G) to produce M = G XOR H on pin 11.
14 VDD power_in Positive supply. Operating range 3 V to 18 V (absolute maximum 20 V). Bypass with a 100 nF ceramic capacitor to VSS close to the pin.

Key specifications

Parameter Value
Type Quad 2-input XOR gate
Logic family 4000B (CMOS)
Gates 4 XOR
Supply voltage 3 V to 18 V
Propagation delay 65 ns typ at 10 V
Operating temperature -55 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • CD4070BBE
  • CD4070BBEE4
  • CD4070BBF
  • CD4070BBF3A
  • CD4070BBF3AS2534
  • CD4070BBM
  • CD4070BBM96
  • CD4070BBME4
  • CD4070BBMG4
  • CD4070BBM96E4
  • CD4070BBM96G4
  • CD4070BBMT
  • CD4070BBMTE4
  • CD4070BBMTG4
  • CD4070BBNSR
  • CD4070BBNSRE4
  • CD4070BBNSRG4
  • CD4070BBPW
  • CD4070BBPWE4
  • CD4070BBPWG4
  • CD4070BBPWR
  • CD4070BBPWRE4
  • CD4070BBPWRG4

CAD (KiCad official)

  • Symbol: cd4070.kicad_sym
  • Footprint: cd4070.kicad_mod
  • 3D model: SOIC-14 body from KiCad Package_SO/SOIC-14_3.9x8.7mm_P1.27mm.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 0a62a1cbf7f15360, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF