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Contents

README

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SN74HC191DR

Texas Instruments · Counters, Dividers · SOIC-16

SN74HC191DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Data input B for parallel load of counter bit 1; active when LOAD is low, allowing the data to be transferred to output QB asynchronously.
2 QB output Counter output bit 1; asynchronously affected by LOAD input data and synchronously affected by CLK when CTEN is low.
3 QA output Counter output bit 0 (least significant bit); asynchronously affected by LOAD input data and synchronously affected by CLK when CTEN is low.
4 CTEN input Count enable input; when low, enables counting; when high, inhibits counting and holds the counter outputs.
5 D/U input Down/up direction control input; when low, counter counts up; when high, counter counts down.
6 QC output Counter output bit 2; asynchronously affected by LOAD input data and synchronously affected by CLK when CTEN is low.
7 QD output Counter output bit 3 (most significant bit); asynchronously affected by LOAD input data and synchronously affected by CLK when CTEN is low.
8 GND power_in Ground reference (0 V connection).
9 D input Data input D for parallel load of counter bit 3 (most significant bit); active when LOAD is low, allowing the data to be transferred to output QD asynchronously.
10 C input Data input C for parallel load of counter bit 2; active when LOAD is low, allowing the data to be transferred to output QC asynchronously.
11 LOAD input Parallel load control input; when low, asynchronously loads data from inputs A, B, C, D into outputs QA, QB, QC, QD, overriding the count operation.
12 MAX/MIN output Maximum/minimum count output; produces a high-level pulse approximately one clock cycle duration when count reaches zero (all outputs low) while counting down or maximum (binary 15) while counting up.
13 RCO output Ripple clock output; produces a low-level pulse under the same conditions as MAX/MIN but only while CLK is low, used for cascading multiple counters.
14 CLK input Clock input; counter outputs change on the low-to-high transition when CTEN is low; operating frequency 2 V to 6 V per recommended operating conditions.
15 A input Data input A for parallel load of counter bit 0 (least significant bit); active when LOAD is low, allowing the data to be transferred to output QA asynchronously.
16 VCC power_in Positive power supply voltage ranging from 2 V to 6 V per recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HC191DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc191dr-etched.step / sn74hc191dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc191dr.step / sn74hc191dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 ca8f1cf1eb9fc572, retrieved 2026-09-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF