component
SIT75179BDR
Public Made by Adomby adom
SIT RS-485/RS-422 ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSIT75179BDR
SIT · RS-485/RS-422 ICs · SOP-8
SIT75179BDR from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Power supply input, 4.5V ≤ VCC ≤ 5.5V. |
| 2 | RO | output | Receiver output: high if A-B ≥ -10mV, low if A-B ≤ -200mV. |
| 3 | DI | input | Driver input: low drives Y low and Z high, high drives Y high and Z low. |
| 4 | GND | power_in | Ground. |
| 5 | Y | output | Driver non-inverting output. |
| 6 | Z | output | Driver inverting output. |
| 7 | B | input | Receiver inverting input. |
| 8 | A | input | Receiver non-inverting input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SIT |
| Package | SOP-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 7 | V | 2 | |||
| Control port voltage (DI) | DI | -0.3 | V | -0.3 to VCC+0.3 | 2 | ||
| Bus input voltage A, B | A, B | -8 | 13 | V | 2 | ||
| Receiver output voltage (RO) | RO | -0.3 | V | -0.3 to VCC+0.3 | 2 | ||
| Operating temperature range | -40 | 125 | °C | 2 | |||
| Storage temperature range | -60 | 150 | °C | 2 | |||
| Soldering temperature | 300 | °C | 2 | ||||
| Continuous power dissipation SOP8 | 400 | mW | SOP8 | 2 | |||
| Supply voltage | VCC | 4.5 | 5.5 | V | 2 | ||
| Driver differential output, no load | VOD1 | 5 | V | no load | 3 | ||
| Driver differential output | VOD2 | 1.5 | 2.3 | V | Fig 2, RL = 27 Ω | 3 | |
| Driver differential output | VOD2 | 2 | 2.8 | V | Fig 2, RL = 50 Ω | 3 | |
| Change in magnitude of output voltage | ΔVOD | 0.2 | V | Fig 2, RL = 27 Ω | 3 | ||
| Output common-mode voltage | VOC | 3 | V | Fig 2, RL = 27 Ω | 3 | ||
| Change in magnitude of common-mode output voltage | ΔVOC | 0.2 | V | Fig 2, RL = 27 Ω | 3 | ||
| High-level input voltage | VIH | 2 | V | DI | 3 | ||
| Low-level input voltage | VIL | 0.8 | V | DI | 3 | ||
| Logic input current | IIN1 | -2 | 2 | uA | DI | 3 | |
| Output short-circuit current, short to high | IOSD1 | 35 | 250 | mA | short to 0V~12V | 3 | |
| Output short-circuit current, short to low | IOSD2 | -250 | -35 | mA | short to -7V~0V | 3 | |
| Input current (A, B) | IIN2 | 125 | uA | VCC=0 or 5V, VIN = 12V | 3 | ||
| Input current (A, B) | IIN2 | -100 | uA | VCC=0 or 5V, VIN = -7 V | 3 | ||
| Positive-going input threshold voltage | VIT+ | -10 | mV | -7V≦VCM≦12V | 3 | ||
| Negative-going input threshold voltage | VIT- | -200 | mV | -7V≦VCM≦12V | 3 | ||
| Input hysteresis voltage | Vhys | 10 | 30 | mV | -7V≦VCM≦12V | 3 | |
| Low-level output voltage | VOL | 0.4 | V | IOUT = +4mA, VID = -200 mV | 4 | ||
| Three-state input leakage current | IOZR | -1 | 1 | uA | 0.4 V < VO < 2.4 V | 4 | |
| Receiver input resistance | RIN | 96 | kΩ | -7V≦VCM≦12V | 4 | ||
| Receiver short-circuit current | IOSR | 7 | 95 | mA | 0 V≤VO≤VCC, printed ±7 to ±95 | 4 | |
| Supply current | ICC | 220 | 400 | uA | DI=0 or VCC | 4 | |
| ESD HBM, A, B, Y, Z | -15 | 15 | KV | Human body model | 4 | ||
| ESD HBM, other pins | -6 | 6 | KV | Human body model | 4 | ||
| Driver propagation delay low to high | tDPLH | 18 | 42 | ns | RDIFF = 54 Ω, CL1=CL2=100pF | 4 | |
| Driver propagation delay high to low | tDPHL | 18 | 42 | ns | RDIFF = 54 Ω, CL1=CL2=100pF | 4 | |
| Driver skew /tDPLH - tDPHL/ | tSKEW1 | 8 | 10 | ns | RDIFF = 54 Ω, CL1=CL2=100pF | 4 | |
| Driver rise/fall time | tDR, tDF | 30 | ns | 5 | |||
| Receiver propagation delay low to high | tRPLH | 30 | 100 | ns | VID≥2.0V; rise and fall time VID≤15ns | 5 | |
| Receiver propagation delay high to low | tRPHL | 30 | 100 | ns | VID≥2.0V; rise and fall time VID≤15ns | 5 | |
| Receiver skew /tRPLH - tRPHL/ | tSKEW2 | 8 | 10 | ns | VID≥2.0V; rise and fall time VID≤15ns | 5 |
CAD (KiCad official)
- Symbol:
SIT75179BDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sit75179bdr-etched.step/sit75179bdr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sit75179bdr.step/sit75179bdr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SIT datasheet (9 pp, sha256
3dae4ebfa9efdde4, retrieved 2026-10-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).