component
STC15F2K32S2-28I-LQFP44
Public Made by Adomby adom
STC Micro Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownSTC15F2K32S2-28I-LQFP44
STC Micro · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STC15F2K32S2-28I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.5/AD5 | bidirectional | Port 0 bit 5, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD5 when the external bus is used. |
| 2 | P0.6/AD6 | bidirectional | Port 0 bit 6, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD6 when the external bus is used. |
| 3 | P0.7/AD7 | bidirectional | Port 0 bit 7, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD7 when the external bus is used. |
| 4 | P1.0/ADC0/CCP1/RxD2 | bidirectional | Standard I/O port P1.0 with ADC input channel 0, CCP1 capture/high-speed output/PWM output, and RxD2 (UART2 receive). |
| 5 | P1.1/ADC1/CCP0/TxD2 | bidirectional | Standard I/O port P1.1 with ADC input channel 1, CCP0 capture/high-speed output/PWM output, and TxD2 (UART2 transmit). |
| 6 | P4.7/TxD2_2 | bidirectional | Standard I/O port P4.7, alternate UART2 transmit output TxD2_2; per the datasheet P4.7 needs a 3.3K pull-up and weak-pull-up/quasi-bidirectional mode when UART2 is switched here. |
| 7 | P1.2/ADC2/SS/ECI | bidirectional | Standard I/O port P1.2 with ADC input channel 2, SPI slave select SS, and CCP/PCA external count input ECI. |
| 8 | P1.3/ADC3/MOSI | bidirectional | Standard I/O port P1.3 with ADC input channel 3 and SPI MOSI (master out / slave in). |
| 9 | P1.4/ADC4/MISO | bidirectional | Standard I/O port P1.4 with ADC input channel 4 and SPI MISO (master in / slave out). |
| 10 | P1.5/ADC5/SCLK | bidirectional | Standard I/O port P1.5 with ADC input channel 5 and SPI serial clock SCLK. |
| 11 | P1.6/ADC6/RxD_3/XTAL2 | bidirectional | Standard I/O port P1.6 with ADC input channel 6, UART1 alternate receive RxD_3, and the XTAL2 crystal amplifier output (may float when an external clock source drives XTAL1). |
| 12 | P1.7/ADC7/TxD_3/XTAL1 | bidirectional | Standard I/O port P1.7 with ADC input channel 7, UART1 alternate transmit TxD_3, and the XTAL1 crystal amplifier input (external clock source input when no crystal is used). |
| 13 | P5.4/RST/MCLKO/SS_3 | bidirectional | Standard I/O port P5.4 by default; can be configured via STC-ISP as RST reset input (high-level reset), or as MCLKO master clock output (MCLK/1, /2, /4) and SPI alternate slave select SS_3. |
| 14 | Vcc | power_in | Positive power supply pin for the device (5.5V to 4.5V for the F-series, 2.4V to 3.6V for the L-series). |
| 15 | P5.5 | bidirectional | Standard I/O port P5.5, which can be used as the comparator positive input CMP+ (set to high-impedance input when used as comparator input). |
| 16 | Gnd | power_in | Ground pin for the device power supply. |
| 17 | P4.0/MOSI_3 | bidirectional | Standard I/O port P4.0 with alternate SPI MOSI output MOSI_3. |
| 18 | P3.0/RxD/INT4/T2CLKO | bidirectional | Standard I/O port P3.0 with UART1 receive RxD, external interrupt INT4 (falling edge only, supports power-down wake-up), and T2 clock output T2CLKO. |
| 19 | P3.1/TxD/T2 | bidirectional | Standard I/O port P3.1 with UART1 transmit TxD and external count input for Timer/Counter 2 (T2). |
| 20 | P3.2/INT0 | bidirectional | Standard I/O port P3.2 with external interrupt INT0 (rising/falling edge, or falling edge only if IT0 is set; supports power-down wake-up). |
| 21 | P3.3/INT1 | bidirectional | Standard I/O port P3.3 with external interrupt INT1 (rising/falling edge, or falling edge only if IT1 is set; supports power-down wake-up). |
| 22 | P3.4/T0/T1CLKO | bidirectional | Standard I/O port P3.4 with Timer 0 external input T0, and Timer 1 clock output T1CLKO (can also divide an external T0 input). |
| 23 | P3.5/T1/T0CLKO | bidirectional | Standard I/O port P3.5 with Timer 1 external input T1 and Timer 0 clock output T0CLKO (can also divide an external T1 input). |
| 24 | P3.6/INT2/RxD_2 | bidirectional | Standard I/O port P3.6 with external interrupt INT2 (falling edge only, supports power-down wake-up) and UART1 alternate receive RxD_2. |
| 25 | P3.7/INT3/TxD_2 | bidirectional | Standard I/O port P3.7 with external interrupt INT3 (falling edge only, supports power-down wake-up) and UART1 alternate transmit TxD_2. |
| 26 | P4.1/MISO_3 | bidirectional | Standard I/O port P4.1 with alternate SPI MISO input MISO_3. |
| 27 | P4.2/WR | bidirectional | Standard I/O port P4.2 with external data memory write strobe WR. |
| 28 | P4.3/SCLK_3 | bidirectional | Standard I/O port P4.3 with alternate SPI serial clock SCLK_3. |
| 29 | P4.4/RD | bidirectional | Standard I/O port P4.4 with external data memory read strobe RD. |
| 30 | P2.0/A8/RSTOUT_LOW | bidirectional | Standard I/O port P2.0 with address bus bit A8; outputs low after power-up and during reset, and can be set high/low by software. |
| 31 | P2.1/A9/SCLK_2 | bidirectional | Standard I/O port P2.1 with address bus bit A9 and alternate SPI clock SCLK_2. |
| 32 | P2.2/A10/MISO_2 | bidirectional | Standard I/O port P2.2 with address bus bit A10 and alternate SPI MISO_2. |
| 33 | P2.3/A11/MOSI_2 | bidirectional | Standard I/O port P2.3 with address bus bit A11 and alternate SPI MOSI_2. |
| 34 | P2.4/A12/ECI_3/SS_2 | bidirectional | Standard I/O port P2.4 with address bus bit A12, CCP/PCA external count input ECI_3, and alternate SPI slave select SS_2. |
| 35 | P2.5/A13/CCP0_3 | bidirectional | Standard I/O port P2.5 with address bus bit A13 and CCP0 alternate capture/high-speed output/PWM channel CCP0_3. |
| 36 | P2.6/A14/CCP1_3 | bidirectional | Standard I/O port P2.6 with address bus bit A14 and CCP1 alternate capture/high-speed output/PWM channel CCP1_3. |
| 37 | P2.7/A15/CCP2_3 | bidirectional | Standard I/O port P2.7 with address bus bit A15 and CCP2 alternate capture/high-speed output/PWM channel CCP2_3. |
| 38 | P4.5/ALE | bidirectional | Standard I/O port P4.5 with address latch enable output ALE. |
| 39 | P4.6/RxD2_2 | bidirectional | Standard I/O port P4.6 with alternate UART2 receive RxD2_2. |
| 40 | P0.0/AD0 | bidirectional | Port 0 bit 0, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD0 when the external bus is used. |
| 41 | P0.1/AD1 | bidirectional | Port 0 bit 1, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD1 when the external bus is used. |
| 42 | P0.2/AD2 | bidirectional | Port 0 bit 2, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD2 when the external bus is used. |
| 43 | P0.3/AD3 | bidirectional | Port 0 bit 3, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD3 when the external bus is used. |
| 44 | P0.4/AD4 | bidirectional | Port 0 bit 4, quasi-bidirectional with weak pull-up after reset, also the multiplexed low-address/data bus line AD4 when the external bus is used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 0 input current (P0,P1,P2,P3) | IIL | 50 | uA | Vpin=0V | 1374 | ||
| Logic 1 to 0 transition current (P0,P1,P2,P3) | ITL | 100 | 270 | 600 | uA | Vpin=2.0V | 1374 |
| Input Low (P0,P1,P2,P3) | VIL1 | 0.8 | V | 5V | 1374 | ||
| Input High (P0,P1,P2,P3) | VIH1 | 2 | V | 5V | 1374 | ||
| Input High (RESET) | VIH2 | 2.2 | V | 5V | 1374 | ||
| Sourcing Current for output high (P0,P1,P2,P3) (Quasi-output) | IOH1 | 200 | 270 | uA | 5V | 1374 | |
| Operating Current | ICC | 4 | 20 | mA | 5V | 1374 | |
| Operating Voltage | VDD | 3.3 | 5 | 5.5 | V | 1374 | |
| Storage temperature | TST | -55 | 125 | ℃ | 1374 | ||
| Operating temperature (I) | TA | -40 | 85 | ℃ | Industrial grade (-I), as used for suffix -28I | 1374 | |
| DC power supply (5V) | VDD - VSS | -0.3 | 5.5 | V | 1374 | ||
| Voltage on any pin | -0.3 | V | Upper limit printed as VCC + 0.3 (not a numeric value) | 1374 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the | 524 |
CAD (KiCad official)
- Symbol:
STC15F2K32S2-28I-LQFP44 - Footprint:
Package_QFP:LQFP-44_10x10mm_P0.8mm - 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
stc15f2k32s2-28i-lqfp44-etched.step/stc15f2k32s2-28i-lqfp44-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc15f2k32s2-28i-lqfp44.step/stc15f2k32s2-28i-lqfp44.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1473 pp, sha256
c1fab41b0006cc18, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).