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DRV8256ERGER

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Texas Instruments Motor Driver ICs, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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DRV8256ERGER

Texas Instruments · Motor Driver ICs · VQFN-24(4x4)

DRV8256ERGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VM power_in Power supply input; connect to motor supply voltage and bypass to PGND with a 0.01-μF ceramic capacitor on each VM pin plus a bulk capacitor rated for VM.
2 PGND power_in Power ground; connect to system ground.
3 OUT1 output Winding output; connect to motor winding.
4 OUT2 output Winding output; connect to motor winding.
5 OUT2 output Winding output; connect to motor winding.
6 OUT1 output Winding output; connect to motor winding.
7 PGND power_in Power ground; connect to system ground.
8 VM power_in Power supply input; connect to motor supply voltage and bypass to PGND with a 0.01-μF ceramic capacitor on each VM pin plus a bulk capacitor rated for VM.
9 GND power_in Device ground; connect to system ground.
10 DVDD power_out Logic supply voltage; connect a X7R 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
11 nFAULT output Fault indication, pulled logic low with a fault condition; open-drain output requires an external pullup resistor.
12 VREF power_in Reference voltage input that sets the full-scale chopping current in the H-bridge; must be tied together with the other VREF pin.
13 VREF power_in Reference voltage input that sets the full-scale chopping current in the H-bridge; must be tied together with the other VREF pin.
14 TOFF input Quad-level pin that sets the decay mode off-time during current chopping and the ripple current in smart tune ripple control mode.
15 NC unconnected No connect.
16 DECAY input Decay mode setting pin; quad-level pin.
17 NC unconnected No connect.
18 NC unconnected No connect.
19 PH input Phase input; logic high drives current from OUT1 to OUT2.
20 EN input Enable input; logic high enables the bridge, logic low disables the bridge Hi-Z.
21 nSLEEP input Sleep mode input; logic high enables the device, logic low enters low-power sleep mode, with internal pulldown resistor.
22 CPL passive Charge pump switching node; connect a X7R 0.022-μF VM-rated ceramic capacitor from CPH to CPL.
23 CPH passive Charge pump switching node; connect a X7R 0.022-μF VM-rated ceramic capacitor from CPH to CPL.
24 VCP power_out Charge pump output; connect a X7R 0.22-μF 16-V ceramic capacitor to VM.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Power Supply Chip
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VM -0.3 50 V 6
Charge pump voltage VCP, CPH -0.3 7 V max is VVM + 7 V 6
nSLEEP pin voltage nSLEEP -0.3 V max is VVM 6
Internal regulator voltage DVDD -0.3 5.75 V 6
Control pin voltage -0.3 5.75 V PH, EN, IN1, IN2, nFAULT, DECAY, TOFF 6
Open drain output current nFAULT 0 10 mA 6
Reference input pin voltage VREF -0.3 5.75 V 6
Continuous phase node pin voltage OUT1, OUT2 -1 1 V max is VVM + 1 V 6
Transient 100 ns phase node pin voltage OUT1, OUT2 -3 3 V max is VVM + 3 V 6
Operating ambient temperature TA -40 125 °C 6
Operating junction temperature TJ -40 150 °C 6
Storage temperature Tstg -65 150 °C 6
Supply voltage range for normal (DC) operation VVM 4.5 48 V 7
Logic level input voltage VI 0 5.5 V 7
Reference rms voltage range VREF 0.05 5 V 7
Applied PWM signal ƒPWM 0 100 kHz PH, EN, IN1, IN2 7
Peak output current IFS 0 6.4 A 7
Operating ambient temperature TA -40 125 °C 7
Operating junction temperature TJ -40 150 °C 7
Junction-to-ambient thermal resistance RθJA 39 °C/W RGE (VQFN) 24 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 28.9 °C/W RGE (VQFN) 24 pins 7
Junction-to-board thermal resistance RθJB 16 °C/W RGE (VQFN) 24 pins 7
Junction-to-top characterization parameter ψJT 0.4 °C/W RGE (VQFN) 24 pins 7
Junction-to-board characterization parameter ψJB 15.9 °C/W RGE (VQFN) 24 pins 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.4 °C/W RGE (VQFN) 24 pins 7
VM operating supply current IVM 4 5.5 mA nSLEEP = 1, No motor load 8
VM sleep mode supply current IVMQ 2 4 μA nSLEEP = 0 8
Sleep time tSLEEP 120 μs nSLEEP = 0 to sleep-mode 8
nSLEEP reset pulse tRESET 20 40 μs nSLEEP low to clear fault 8
Wake-up time tWAKE 0.8 1.2 ms nSLEEP = 1 to output transition 8
Turn-on time tON 0.8 1.2 ms VM > UVLO to output transition 8
Internal regulator voltage VDVDD 4.75 5 5.25 V No external load, 6 V < VVM < 48 V 8
Internal regulator voltage VDVDD 4.2 4.35 V No external load, VVM = 4.5V 8
Input logic-low voltage VIL 0 0.6 V 8
Input logic-high voltage VIH 1.5 5.5 V 8
Input logic-low current IIL -1 1 μA VIN = 0 V 8
Input logic-high current IIH 100 μA VIN = 5 V 8
Propagation delay tPD 800 ns PH, EN, INx input to current change 8
Input logic-low voltage (quad-level) VI1 0 0.6 V Tied to GND 8
Quad-level input voltage VI2 1 1.25 1.4 V 330kΩ ± 5% to GND 8
Input Hi-Z voltage VI3 1.8 2 2.2 V Hi-Z (>500kΩ to GND) 8
Input logic-high voltage (quad-level) VI4 2.7 5.5 V Tied to DVDD 8
Output logic-low voltage VOL 0.5 V IO = 5 mA 8
Output logic-high leakage IOH -1 1 μA 8
High-side FET on resistance RDS(ONH) 82 100 mΩ TJ = 25 °C, IO = -1 A 8
High-side FET on resistance RDS(ONH) 125 150 mΩ TJ = 125 °C, IO = -1 A 8
High-side FET on resistance RDS(ONH) 140 175 mΩ TJ = 150 °C, IO = -1 A 8
Low-side FET on resistance RDS(ONL) 82 100 mΩ TJ = 25 °C, IO = 1 A 8
Low-side FET on resistance RDS(ONL) 125 150 mΩ TJ = 125 °C, IO = 1 A 8
Low-side FET on resistance RDS(ONL) 140 175 mΩ TJ = 150 °C, IO = 1 A 8
ITRIP Current Accuracy ΔITRIP -12 12 % 0.5 A < ITRIP < 1 A 9
ITRIP Current Accuracy ΔITRIP -6 6 % 1 A < ITRIP < 2 A 9
ITRIP Current Accuracy ΔITRIP -4 4 % 2 A < ITRIP < 5 A 9
VM UVLO lockout, falling VUVLO 4.1 4.25 4.35 V VM falling, UVLO falling 9
VM UVLO lockout, rising VUVLO 4.2 4.35 4.45 V VM rising, UVLO rising 9
Thermal shutdown TOTSD 150 165 180 °C Die temperature TJ 9
Overcurrent protection IOCP 8 A Current through any FET 9
Overcurrent deglitch time tOCP 2 μs 9
Output slew rate tSR 240 V/µs VM = 24V, IO = 1 A, Between 10% and 90% 8
VREF Leakage Current IVREF 8.25 μA VREF = 3.3 V 8

CAD (KiCad official)

  • Symbol: DRV8256ERGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: drv8256erger-etched.step / drv8256erger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8256erger.step / drv8256erger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 bd58d759d6feafad, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF