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DAC8532IDGK

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Texas Instruments Digital To Analog Converters (DAC), VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitiondac8532idgkfactory-2.0.0extractor-text

Verified DAC8532IDGK

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC8532IDGK · VSSOP-8-0.65mm · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C1554588, digikey DAC8532IDGK-ND, mouser 595-DAC8532IDGK
  • ✓family: VSSOP-8_2.3x2mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-fj0vdt0e/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac8532idgk.kicad_sym✓ dac8532idgk.kicad_mod✓ dac8532idgk.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

DAC8532IDGK

Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-8-0.65mm

DAC8532IDGK from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input, specified from 2.7 V to 5.5 V.
2 VREF power_in Reference voltage input that sets the output range of each DAC channel.
3 VOUTB output Analog output voltage from DAC B.
4 VOUTA output Analog output voltage from DAC A.
5 SYNC input Level-triggered active-LOW frame synchronization input; the write is executed following the 24th falling SCLK edge unless SYNC is taken HIGH before that edge, in which case the write is ignored.
6 SCLK input Serial clock input supporting data transfer rates up to 30 MHz at 5 V.
7 DIN input Serial data input clocked into the 24-bit input shift register on the falling edge of the serial clock.
8 GND power_in Ground reference point for all circuitry on the part.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8-0.65mm
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD to GND VDD -0.3 6 V 3
Operating temperature range -40 105 °C 3
Storage temperature range Tstg -65 150 °C 3
Junction temperature TJ 150 °C 3
VDD to GND VDD 0 5.5 V 4
Operating temperature range -40 105 °C all specifications 4
Relative accuracy -0.0987 0.0987 % of FSR 4
Differential nonlinearity -1 1 LSB 16-bit monotonic 4
Zero code error 5 25 mV 4
Full-scale error -0.15 -1 % of FSR 4
Gain error -1 1 % of FSR 4
Zero code error drift -20 20 µV/°C 4
Gain temperature coefficient -5 5 ppm of FSR/°C 4
Output voltage settling time 8 10 µs To ±0.003% FSR; 0200H to FD00H, RL = 2 kΩ, 0 pF < CL < 200 pF 4
AC crosstalk -100 -96 dB 4
Reference current 67 90 µA VREF = VDD = 5 V 5
Reference current 40 54 µA VREF = VDD = 3 V 5
Input current -1 1 µA 5
Input LOW voltage VINL 0.8 V VDD = 5 V 5
Input LOW voltage VINL 0.6 V VDD = 3 V 5
Input HIGH voltage VINH 2.4 V VDD = 5 V 5
Input HIGH voltage VINH 2.1 V VDD = 3 V 5
Supply voltage VDD 2.7 5.5 V 5
IDD (normal mode) IDD 500 800 µA VDD = 3.6 V to 5.5 V; DAC active and excluding load current 5
IDD (normal mode) IDD 450 750 µA VDD = 2.7 V to 3.6 V; DAC active and excluding load current 5
IDD (all power-down modes) IDD 0.2 1 µA VDD = 3.6 V to 5.5 V; VIH = VDD and VIL = GND 5
IDD (all power-down modes) IDD 0.05 1 µA VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND 5
SCLK cycle time t1 50 ns VDD = 2.7 V to 3.6 V 6
SCLK cycle time t1 33 ns VDD = 3.6 V to 5.5 V 6
SCLK HIGH time t2 13 ns VDD = 2.7 V to 3.6 V 6
SCLK LOW time t3 22.5 ns VDD = 2.7 V to 3.6 V 6
SCLK LOW time t3 13 ns VDD = 3.6 V to 5.5 V 6
SYNC to SCLK rising edge setup time t4 0 ns VDD = 2.7 V to 3.6 V 6
Data setup time t5 5 ns VDD = 2.7 V to 3.6 V 6
Data hold time t6 4.5 ns VDD = 2.7 V to 3.6 V 6
24th SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 3.6 V 6
Minimum SYNC HIGH time t8 50 ns VDD = 2.7 V to 3.6 V 6
Minimum SYNC HIGH time t8 33 ns VDD = 3.6 V to 5.5 V 6
24th SCLK falling edge to SYNC falling edge t9 100 ns VDD = 2.7 V to 5.5 V 6
Slew rate 1 V/µs 4
Code change glitch impulse 20 nV-s 4
Digital feedthrough 0.5 nV-s 4
DC crosstalk 0.25 LSB 1 LSB change around major carry 4
DC output impedance 1 Ω 4
Short circuit current 50 mA VDD = 5 V 4
Short circuit current 20 mA VDD = 3 V 4
Power-up time 2.5 µs Coming out of power-down mode, VDD = 5 V 5
Power-up time 5 µs Coming out of power-down mode, VDD = 3 V 5
Power efficiency IOUT/IDD 89 % ILOAD = 2 mA, VDD = 5 V 5
Reference input impedance 75 kΩ 5
Pin capacitance 3 pF 5
Capacitive load stability 470 pF RL = ∞ 4
Capacitive load stability 1000 pF RL = 2 kΩ 4
Signal-to-noise ratio (SNR) 94 dB BW = 20 kHz, VDD = 5 V, FOUT = 1 kHz 5

CAD (KiCad official)

  • Symbol: DAC8532IDGK
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
  • 3D model files: dac8532idgk-etched.step / dac8532idgk-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8532idgk.step / dac8532idgk.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 0b3ba867ec2d63e2, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF