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Contents

README

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STM32F469IIT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-176(24x24)

STM32F469IIT6 from STMicroelectronics, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional Port E pin 2; can be configured as TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, ETH_MII_TXD3, FMC_A23, or general-purpose I/O.
2 PE3 bidirectional Port E pin 3; can be configured as TRACED0, SAI1_SD_B, FMC_A19, or general-purpose I/O.
3 PE4 bidirectional Port E pin 4; can be configured as TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, LCD_B0, or general-purpose I/O.
4 PE5 bidirectional Port E pin 5; can be configured as TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, LCD_G0, or general-purpose I/O.
5 PE6 bidirectional Port E pin 6; can be configured as TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, LCD_G1, or general-purpose I/O.
6 VBAT power_in Supply voltage for RTC, backup SRAM, and backup registers, typically connected to battery or VDD.
7 PI8 bidirectional Port I pin 8; can be configured as RTC_TAMP1/RTC_TAMP2/RTC_TS or general-purpose I/O; supplied through power switch with 3 mA limit.
8 PC13 bidirectional Port C pin 13; can be configured as RTC_TAMP1/RTC_TS/RTC_OUT or general-purpose I/O; supplied through power switch with 3 mA limit.
9 PC14/OSC32_IN bidirectional Port C pin 14 / 32 kHz oscillator input; default function is OSC32_IN; can be configured as general-purpose I/O; supplied through power switch with 3 mA limit.
10 PC15/OSC32_OUT bidirectional Port C pin 15 / 32 kHz oscillator output; default function is OSC32_OUT; can be configured as general-purpose I/O; supplied through power switch with 3 mA limit.
11 PI9 bidirectional Port I pin 9; can be configured as CAN1_RX, FMC_D30, LCD_VSYNC, or general-purpose I/O.
12 PI10 bidirectional Port I pin 10; can be configured as ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, or general-purpose I/O.
13 PI11 bidirectional Port I pin 11; can be configured as LCD_G6, OTG_HS_ULPI_DIR, or general-purpose I/O.
14 VSS power_in Ground reference.
15 VDD power_in Supply voltage 1.7 V to 3.6 V.
16 PF0 bidirectional
17 PF1 bidirectional
18 PF2 bidirectional
19 PF3 bidirectional Port F pin 3; can be configured as FMC_A3 or general-purpose I/O; ADC3_IN9 analog input.
20 PF4 bidirectional Port F pin 4; can be configured as FMC_A4 or general-purpose I/O; ADC3_IN14 analog input.
21 PF5 bidirectional Port F pin 5; can be configured as FMC_A5 or general-purpose I/O; ADC3_IN15 analog input.
22 VSS power_in Ground reference.
23 VDD power_in Supply voltage 1.7 V to 3.6 V.
24 PF6 bidirectional Port F pin 6; can be configured as TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_Rx, QUADSPI_BK1_IO3, or general-purpose I/O; ADC3_IN4 analog input.
25 PF7 bidirectional Port F pin 7; can be configured as TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_Tx, QUADSPI_BK1_IO2, or general-purpose I/O; ADC3_IN5 analog input.
26 PF8 bidirectional Port F pin 8; can be configured as SPI5_MISO, SAI1_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, or general-purpose I/O; ADC3_IN6 analog input.
27 PF9 bidirectional Port F pin 9; can be configured as SPI5_MOSI, SAI1_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, or general-purpose I/O; ADC3_IN7 analog input.
28 PF10 bidirectional Port F pin 10; can be configured as QUADSPI_CLK, DCMI_D11, LCD_DE, or general-purpose I/O; ADC3_IN8 analog input.
29 PH0/OSC_IN bidirectional Port H pin 0 / high-speed oscillator input; default function is OSC_IN; can be configured as general-purpose I/O.
30 PH1/OSC_OUT bidirectional Port H pin 1 / high-speed oscillator output; default function is OSC_OUT; can be configured as general-purpose I/O.
31 NRST input Active-low reset input with internal weak pull-up; assert reset when pulled below VRST(L) threshold; used for system reset control.
32 PC0 bidirectional Port C pin 0; can be configured as OTG_HS_ULPI_STP, FMC_SDNWE, LCD_R5, or general-purpose I/O; ADC123_IN10 analog input.
33 PC1 bidirectional Port C pin 1; can be configured as TRACED0, SPI2_MOSI/I2S2_SD, SAI1_SD_A, ETH_MDC, or general-purpose I/O; ADC123_IN11 analog input.
34 PC2 bidirectional Port C pin 2; can be configured as SPI2_MISO, I2S2ext_SD, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, or general-purpose I/O; ADC123_IN12 analog input.
35 PC3 bidirectional Port C pin 3; can be configured as SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, or general-purpose I/O; ADC123_IN13 analog input.
36 VDD power_in Supply voltage 1.7 V to 3.6 V.
37 VSSA power_in Analog ground reference for ADC.
38 VREF+ power_in ADC reference voltage positive input; 1.62 V to 3.6 V; decoupled with 100 nF capacitor.
39 VDDA power_in Analog supply voltage for ADC and comparators; 1.62 V to 3.6 V.
40 PA0/WKUP bidirectional Port A pin 0 / wakeup pin; can be configured as TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, ETH_MII_CRS, or general-purpose I/O; ADC123_IN0 analog input; wakeup from low-power modes.
41 PA1 bidirectional Port A pin 1; can be configured as TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, ETH_MII_RX_CLK/ETH_RMII_REF_CLK, LCD_R2, or general-purpose I/O; ADC123_IN1 analog input.
42 PA2 bidirectional Port A pin 2; can be configured as TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, ETH_MDIO, LCD_R1, or general-purpose I/O; ADC123_IN2 analog input.
43 PH2 bidirectional Port H pin 2; can be configured as QUADSPI_BK2_IO0, ETH_MII_CRS, FMC_SDCKE0, LCD_R0, or general-purpose I/O.
44 PH3 bidirectional Port H pin 3; can be configured as QUADSPI_BK2_IO1, ETH_MII_COL, FMC_SDNE0, LCD_R1, or general-purpose I/O.
45 PH4 bidirectional Port H pin 4; can be configured as I2C2_SCL, LCD_G5, OTG_HS_ULPI_NXT, LCD_G4, or general-purpose I/O.
46 PH5 bidirectional Port H pin 5; can be configured as I2C2_SDA, SPI5_NSS, FMC_SDNWE, or general-purpose I/O.
47 PA3 bidirectional Port A pin 3; can be configured as TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, LCD_B2, OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, or general-purpose I/O; ADC123_IN3 analog input.
48 BYPASS_REG input
49 VDD power_in Supply voltage 1.7 V to 3.6 V.
50 PA4 bidirectional Port A pin 4; can be configured as SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, or general-purpose I/O; ADC12_IN4 analog input; DAC_OUT1 analog output.
51 PA5 bidirectional Port A pin 5; can be configured as TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK, OTG_HS_ULPI_CK, LCD_R4, or general-purpose I/O; ADC12_IN5 analog input; DAC_OUT2 analog output.
52 PA6 bidirectional Port A pin 6; can be configured as TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM13_CH1, DCMI_PIXCLK, LCD_G2, or general-purpose I/O; ADC12_IN6 analog input.
53 PA7 bidirectional Port A pin 7; can be configured as TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM14_CH1, QUADSPI_CLK, ETH_MII_RX_DV/ETH_RMII_CRS_DV, FMC_SDNWE, or general-purpose I/O; ADC12_IN7 analog input.
54 PC4 bidirectional
55 PC5 bidirectional
56 PB0 bidirectional Port B pin 0; can be configured as TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, LCD_G1, or general-purpose I/O; ADC12_IN8 analog input.
57 PB1 bidirectional Port B pin 1; can be configured as TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, or general-purpose I/O; ADC12_IN9 analog input.
58 PB2/BOOT1 bidirectional Port B pin 2 / boot configuration pin; can be configured as general-purpose I/O.
59 PF11 bidirectional Port F pin 11; can be configured as SPI5_MOSI, FMC_SDNRAS, DCMI_D12, or general-purpose I/O.
60 PF12 bidirectional Port F pin 12; can be configured as FMC_A6 or general-purpose I/O.
61 VSS power_in Ground reference.
62 VDD power_in Supply voltage 1.7 V to 3.6 V.
63 PF13 bidirectional Port F pin 13; can be configured as FMC_A7 or general-purpose I/O.
64 PF14 bidirectional Port F pin 14; can be configured as FMC_A8 or general-purpose I/O.
65 PF15 bidirectional Port F pin 15; can be configured as FMC_A9 or general-purpose I/O.
66 PG0 bidirectional Port G pin 0; can be configured as FMC_A10 or general-purpose I/O.
67 PG1 bidirectional Port G pin 1; can be configured as FMC_A11 or general-purpose I/O.
68 PE7 bidirectional Port E pin 7; can be configured as TIM1_ETR, UART7_Rx, QUADSPI_BK2_IO0, FMC_D4, or general-purpose I/O.
69 PE8 bidirectional Port E pin 8; can be configured as TIM1_CH1N, UART7_Tx, QUADSPI_BK2_IO1, FMC_D5, or general-purpose I/O.
70 PE9 bidirectional Port E pin 9; can be configured as TIM1_CH1, QUADSPI_BK2_IO2, FMC_D6, or general-purpose I/O.
71 VSS power_in Ground reference.
72 VDD power_in Supply voltage 1.7 V to 3.6 V.
73 PE10 bidirectional Port E pin 10; can be configured as TIM1_CH2N, QUADSPI_BK2_IO3, FMC_D7, or general-purpose I/O.
74 PE11 bidirectional Port E pin 11; can be configured as TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3, or general-purpose I/O.
75 PE12 bidirectional Port E pin 12; can be configured as TIM1_CH3N, SPI4_SCK, FMC_D9, LCD_B4, or general-purpose I/O.
76 PE13 bidirectional Port E pin 13; can be configured as TIM1_CH3, SPI4_MISO, FMC_D10, LCD_DE, or general-purpose I/O.
77 PE14 bidirectional Port E pin 14; can be configured as TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK, or general-purpose I/O.
78 PE15 bidirectional Port E pin 15; can be configured as TIM1_BKIN, FMC_D12, LCD_R7, or general-purpose I/O.
79 PB10 bidirectional Port B pin 10; can be configured as TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, QUADSPI_BK1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, or general-purpose I/O.
80 PB11 bidirectional Port B pin 11; can be configured as TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_TX_EN, DSIHOST_TE, LCD_G5, or general-purpose I/O.
81 VCAP1 power_in Decoupling capacitor pin for core voltage regulator; connect 4.7 µF ceramic capacitor to ground.
82 VDD power_in Supply voltage 1.7 V to 3.6 V.
83 PH6 bidirectional Port H pin 6; can be configured as I2C2_SMBA, SPI5_SCK, TIM12_CH1, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, or general-purpose I/O.
84 PH7 bidirectional Port H pin 7; can be configured as I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, or general-purpose I/O.
85 PB12 bidirectional Port B pin 12; can be configured as TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OTG_HS_ID, or general-purpose I/O.
86 PB13 bidirectional Port B pin 13; can be configured as TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, or general-purpose I/O; OTG_HS_VBUS analog input.
87 PB14 bidirectional Port B pin 14; can be configured as TIM1_CH2N, TIM8_CH2N, SPI2_MISO, I2S2ext_SD, USART3_RTS, TIM12_CH1, OTG_HS_DM, or general-purpose I/O.
88 PB15 bidirectional Port B pin 15; can be configured as RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, or general-purpose I/O.
89 PD8 bidirectional Port D pin 8; can be configured as USART3_TX, FMC_D13, or general-purpose I/O.
90 PD9 bidirectional Port D pin 9; can be configured as USART3_RX, FMC_D14, or general-purpose I/O.
91 PD10 bidirectional Port D pin 10; can be configured as USART3_CK, FMC_D15, LCD_B3, or general-purpose I/O.
92 PD11 bidirectional Port D pin 11; can be configured as USART3_CTS, QUADSPI_BK1_IO0, FMC_A16/FMC_CLE, or general-purpose I/O.
93 PD12 bidirectional Port D pin 12; can be configured as TIM4_CH1, USART3_RTS, QUADSPI_BK1_IO1, FMC_A17/FMC_ALE, or general-purpose I/O.
94 PD13 bidirectional Port D pin 13; can be configured as TIM4_CH2, QUADSPI_BK1_IO3, FMC_A18, or general-purpose I/O.
95 VSS power_in Ground reference.
96 VDD power_in Supply voltage 1.7 V to 3.6 V.
97 PD14 bidirectional Port D pin 14; can be configured as TIM4_CH3, FMC_D0, or general-purpose I/O.
98 PD15 bidirectional Port D pin 15; can be configured as TIM4_CH4, FMC_D1, or general-purpose I/O.
99 VDDDSI power_in DSI host supply voltage.
100 VCAPDSI power_in DSI host regulator decoupling capacitor pin.
101 DSIHOST_D0P bidirectional MIPI DSI host data lane 0 positive signal.
102 DSIHOST_D0N bidirectional MIPI DSI host data lane 0 negative signal.
103 VSSDSI power_in DSI ground reference.
104 DSIHOST_CKP bidirectional MIPI DSI host clock lane positive signal.
105 DSIHOST_CKN bidirectional MIPI DSI host clock lane negative signal.
106 VDD12DSI power_in DSI 1.2 V internal regulator output and PLL supply voltage.
107 DSIHOST_D1P bidirectional MIPI DSI host data lane 1 positive signal.
108 DSIHOST_D1N bidirectional MIPI DSI host data lane 1 negative signal.
109 VSSDSI power_in DSI ground reference.
110 PG2 bidirectional Port G pin 2; can be configured as FMC_A12 or general-purpose I/O.
111 PG3 bidirectional Port G pin 3; can be configured as FMC_A13 or general-purpose I/O.
112 PG4 bidirectional Port G pin 4; can be configured as FMC_A14/FMC_BA0 or general-purpose I/O.
113 PG5 bidirectional Port G pin 5; can be configured as FMC_A15/FMC_BA1 or general-purpose I/O.
114 PG6 bidirectional Port G pin 6; can be configured as DCMI_D12, LCD_R7, or general-purpose I/O.
115 PG7 bidirectional Port G pin 7; can be configured as SAI1_MCLK_A, USART6_CK, FMC_INT, DCMI_D13, LCD_CLK, or general-purpose I/O.
116 PG8 bidirectional Port G pin 8; can be configured as SPI6_NSS, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, or general-purpose I/O.
117 VSS power_in Ground reference.
118 VDDUSB power_in USB dedicated supply voltage (1.62 V to 3.6 V); can be independent from VDD for full-speed operation.
119 PC6 bidirectional Port C pin 6; can be configured as TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, LCD_HSYNC, or general-purpose I/O.
120 PC7 bidirectional Port C pin 7; can be configured as TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDIO_D7, DCMI_D1, LCD_G6, or general-purpose I/O.
121 PC8 bidirectional Port C pin 8; can be configured as TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, SDIO_D0, DCMI_D2, or general-purpose I/O.
122 PC9 bidirectional Port C pin 9; can be configured as MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, QUADSPI_BK1_IO0, SDIO_D1, DCMI_D3, or general-purpose I/O.
123 PA8 bidirectional Port A pin 8; can be configured as MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, LCD_R6, or general-purpose I/O.
124 PA9 bidirectional Port A pin 9; can be configured as TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, DCMI_D0, or general-purpose I/O; OTG_FS_VBUS analog input.
125 PA10 bidirectional Port A pin 10; can be configured as TIM1_CH3, USART1_RX, OTG_FS_ID, DCMI_D1, or general-purpose I/O.
126 PA11 bidirectional Port A pin 11; can be configured as TIM1_CH4, USART1_CTS, CAN1_RX, OTG_FS_DM, LCD_R4, or general-purpose I/O.
127 PA12 bidirectional Port A pin 12; can be configured as TIM1_ETR, USART1_RTS, CAN1_TX, OTG_FS_DP, LCD_R5, or general-purpose I/O.
128 PA13 bidirectional
129 VCAP2 power_in Decoupling capacitor pin for core voltage regulator; connect 4.7 µF ceramic capacitor to ground.
130 VSS power_in Ground reference.
131 VDD power_in Supply voltage 1.7 V to 3.6 V.
132 PI0 bidirectional Port I pin 0; can be configured as TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, DCMI_D13, LCD_G5, or general-purpose I/O.
133 PI1 bidirectional Port I pin 1; can be configured as SPI2_SCK/I2S2_CK, FMC_D25, DCMI_D8, LCD_G6, or general-purpose I/O.
134 PI3 bidirectional Port I pin 3; can be configured as TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, DCMI_D10, or general-purpose I/O.
135 VSS power_in Ground reference.
136 VDD power_in Supply voltage 1.7 V to 3.6 V.
137 PA14 bidirectional
138 PA15 bidirectional
139 PC10 bidirectional Port C pin 10; can be configured as SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDIO_D2, DCMI_D8, LCD_R2, or general-purpose I/O.
140 PC11 bidirectional Port C pin 11; can be configured as I2S3ext_SD, SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDIO_D3, DCMI_D4, or general-purpose I/O.
141 PC12 bidirectional Port C pin 12; can be configured as TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, or general-purpose I/O.
142 PD0 bidirectional Port D pin 0; can be configured as CAN1_RX, FMC_D2, or general-purpose I/O.
143 PD1 bidirectional Port D pin 1; can be configured as CAN1_TX, FMC_D3, or general-purpose I/O.
144 PD2 bidirectional
145 PD3 bidirectional
146 PD4 bidirectional
147 PD5 bidirectional
148 VSS power_in Ground reference.
149 VDD power_in Supply voltage 1.7 V to 3.6 V.
150 PD6 bidirectional
151 PD7 bidirectional
152 PG9 bidirectional Port G pin 9; can be configured as USART6_RX, QUADSPI_BK2_IO2, FMC_NE2/FMC_NCE, DCMI_VSYNC, or general-purpose I/O.
153 PG10 bidirectional Port G pin 10; can be configured as LCD_G3, FMC_NE3, DCMI_D2, LCD_B2, or general-purpose I/O.
154 PG11 bidirectional Port G pin 11; can be configured as ETH_MII_TX_EN/ETH_RMII_TX_EN, DCMI_D3, LCD_B3, or general-purpose I/O.
155 PG12 bidirectional Port G pin 12; can be configured as SPI6_MISO, USART6_RTS, LCD_B4, FMC_NE4, LCD_B1, or general-purpose I/O.
156 PG13 bidirectional Port G pin 13; can be configured as TRACED0, SPI6_SCK, USART6_CTS, ETH_MII_TXD0/ETH_RMII_TXD0, FMC_A24, LCD_R0, or general-purpose I/O.
157 PG14 bidirectional Port G pin 14; can be configured as TRACED1, SPI6_MOSI, USART6_TX, QUADSPI_BK2_IO3, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_A25, LCD_B0, or general-purpose I/O.
158 VSS power_in Ground reference.
159 VDD power_in Supply voltage 1.7 V to 3.6 V.
160 PG15 bidirectional
161 PB3 bidirectional
162 PB4 bidirectional
163 PB5 bidirectional
164 PB6 bidirectional
165 PB7 bidirectional
166 BOOT0 input
167 PB8 bidirectional
168 PB9 bidirectional
169 PE0 bidirectional
170 PE1 bidirectional
171 PDR_ON input
172 VDD power_in Supply voltage 1.7 V to 3.6 V.
173 PI4 bidirectional Port I pin 4; can be configured as TIM8_BKIN, FMC_NBL2, DCMI_D5, LCD_B4, or general-purpose I/O.
174 PI5 bidirectional Port I pin 5; can be configured as TIM8_CH1, FMC_NBL3, DCMI_VSYNC, LCD_B5, or general-purpose I/O.
175 PI6 bidirectional Port I pin 6; can be configured as TIM8_CH2, FMC_D28, DCMI_D6, LCD_B6, or general-purpose I/O.
176 PI7 bidirectional Port I pin 7; can be configured as TIM8_CH3, FMC_D29, DCMI_D7, LCD_B7, or general-purpose I/O.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-176(24x24)
Category Embedded Processors & Controllers
Pins 176

CAD (KiCad official)

  • Symbol: STM32F469IIT6
  • Footprint: Package_QFP:LQFP-176_24x24mm_P0.5mm
  • 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
  • 3D model files: stm32f469iit6-etched.step / stm32f469iit6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f469iit6.step / stm32f469iit6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (217 pp, sha256 0a93578085d53c67, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF