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Contents

README

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MCP6002DRG

HANSCHIP semiconductor · Operational Amplifier · SOP-8

MCP6002DRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Output of op-amp A. Rail-to-rail output swing; source/sink current approximately 84mA/75mA (typ) into 10Ω to VS/2.
2 VINA- input Inverting input of op-amp A. Analog input voltage range Vss-0.5V to VDD+0.5V (abs max); common-mode range -0.1V to +5.6V at VS=5.5V.
3 VINA+ input Non-inverting input of op-amp A. Rail-to-rail input; input bias current ~1pA (typ), input offset current ~1pA (typ).
4 VSS power_in Negative supply / ground reference. Power supply range VDD-VSS = 1.8V to 6V (abs max -0.5V to +7.5V).
5 VINB+ input Non-inverting input of op-amp B. Rail-to-rail input; input bias current ~1pA (typ).
6 VINB- input Inverting input of op-amp B. Analog input voltage range Vss-0.5V to VDD+0.5V (abs max).
7 VOUTB output Output of op-amp B. Rail-to-rail output swing; VOH within ~5mV of VDD and VOL within ~5mV of VSS at RL=100kΩ.
8 VDD power_in Positive supply. Operating range +1.8V to +6V referenced to VSS; quiescent current 75µA/amplifier (typ), 125µA/amplifier (max).

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • MCP6002DRG
  • MCP6002DRG4
  • MCP6002DRGDGKRG

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage VOS 0.8 3.5 mV VCM = VS/2, +25℃ 4
Input Offset Voltage VOS 5.6 mV VCM = VS/2, -40℃ to +85℃ 4
Common-Mode Rejection Ratio CMRR 62 70 dB VS = 5.5V, VCM = -0.1V to 4V, +25℃ 4
Common-Mode Rejection Ratio CMRR 62 dB VS = 5.5V, VCM = -0.1V to 4V, -40℃ to +85℃ 4
Common-Mode Rejection Ratio CMRR 56 68 dB VS = 5.5V, VCM = -0.1V to 5.6V, +25℃ 4
Common-Mode Rejection Ratio CMRR 55 dB VS = 5.5V, VCM = -0.1V to 5.6V, -40℃ to +85℃ 4
Open-Loop Voltage Gain AOL 70 80 dB RL = 5kΩ, VO = +0.1V to +4.9V, +25℃ 4
Open-Loop Voltage Gain AOL 70 dB RL = 5kΩ, VO = +0.1V to +4.9V, -40℃ to +85℃ 4
Open-Loop Voltage Gain AOL 94 100 dB RL = 10kΩ, VO = +0.1V to +4.9V, +25℃ 4
Open-Loop Voltage Gain AOL 85 dB RL = 10kΩ, VO = +0.1V to +4.9V, -40℃ to +85℃ 4
Output Voltage Swing from Rail (high) VOH 4.98 4.997 V RL = 100kΩ, +25℃ 4
Output Voltage Swing from Rail (high) VOH 4.97 V RL = 100kΩ, -40℃ to +85℃ 4
Output Voltage Swing from Rail (low) VOL 5 20 mV RL = 100kΩ, +25℃ 4
Output Voltage Swing from Rail (low) VOL 30 mV RL = 100kΩ, -40℃ to +85℃ 4
Output Voltage Swing from Rail (high) VOH 4.97 4.992 V RL = 10kΩ, +25℃ 4
Output Voltage Swing from Rail (high) VOH 4.96 V RL = 10kΩ, -40℃ to +85℃ 4
Output Voltage Swing from Rail (low) VOL 8 30 mV RL = 10kΩ, +25℃ 4
Output Voltage Swing from Rail (low) VOL 40 mV RL = 10kΩ, -40℃ to +85℃ 4
Output Current (source) ISOURCE 60 84 mA RL = 10Ω to VS/2, +25℃ 4
Output Current (source) ISOURCE 45 mA RL = 10Ω to VS/2, -40℃ to +85℃ 4
Output Current (sink) ISINK 60 75 mA RL = 10Ω to VS/2, +25℃ 4
Output Current (sink) ISINK 45 mA RL = 10Ω to VS/2, -40℃ to +85℃ 4
Operating Voltage Range 1.8 V 4
Operating Voltage Range 6 V 4
Power Supply Rejection Ratio PSRR 60 82 dB VS = +2.5V to +6V, VCM = +0.5V, +25℃ 4
Power Supply Rejection Ratio PSRR 58 dB VS = +2.5V to +6V, VCM = +0.5V, -40℃ to +85℃ 4
Quiescent Current / Amplifier IQ 75 110 µA +25℃ 4
Quiescent Current / Amplifier IQ 125 µA -40℃ to +85℃ 4
Power Supply Voltage (VDD to Vss) -0.5 7.5 V VDD to Vss 3
PDB Input Voltage 7 V Vss-0.5V to +7V 3
Operating Temperature Range -40 125 °C 3
Junction Temperature 160 °C 3
Storage Temperature Range -55 150 °C 3
Lead Temperature 245 °C soldering, 10sec 3
Package Thermal Resistance, SOP-8 θJA 125 °C/W TA=+25℃, SOP-8 3
ESD Susceptibility HBM 6 KV HBM 3
ESD Susceptibility MM 400 V MM 3

CAD (KiCad official)

  • Symbol: MCP6002DRG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: mcp6002drg-etched.step / mcp6002drg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp6002drg.step / mcp6002drg.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
mcp6002drg.step 122 KB You want the bare part, or you mark your own boards.
mcp6002drg-etched.step 2.4 MB You want the part with MCP6002DRG already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 573 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (14 pp, sha256 c4edb1ba02979bc5, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF