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DAC8162SDSCR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC8162SDSCR
Texas Instruments · Digital To Analog Converters (DACs) · WSON-10-EP(3x3)
DAC8162SDSCR from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A; absolute maximum VOUT[A,B] to GND is -0.3 V to AVDD + 0.3 V. |
| 2 | VOUTB | output | Analog output voltage from DAC-B; absolute maximum VOUT[A,B] to GND is -0.3 V to AVDD + 0.3 V. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Must be connected to GND permanently or held low before commands are sent in synchronous mode, and acts as a negative edge-triggered signal for simultaneous DAC updates in asynchronous mode. |
| 5 | CLR | input | Falling-edge sensitive asynchronous clear input that loads zero scale (DACxx62) to all input and DAC registers; the device exits clear mode on the 24th falling edge of the next write. |
| 6 | SYNC | input | Active-low level-triggered frame sync input (Schmitt-trigger); the DAC output updates after the 24th SCLK falling edge, and a SYNC rising edge before the 23rd clock edge interrupts and discards the write. |
| 7 | SCLK | input | Serial clock input (Schmitt-trigger) supporting data transfer at rates up to 50 MHz. |
| 8 | DIN | input | Serial data input (Schmitt-trigger) clocked into the 24-bit input shift register on each falling edge of SCLK. |
| 9 | AVDD | power_in | Power-supply input, 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin: 2.5-V output when the internal reference is used, otherwise an input with reference voltage range 0 V to AVDD. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 11 |
CAD (KiCad official)
- Symbol:
DAC8162SDSCR - Footprint:
Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm - 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
dac8162sdscr-etched.step/dac8162sdscr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8162sdscr.step/dac8162sdscr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
3fbba20baac4cf7e, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).