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sn74hct373pwr

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by Ray

Texas Instruments Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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SN74HCT373PWR

Texas Instruments · Latches · TSSOP-20

SN74HCT373PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output Enable, active LOW. When LOW, the 3-state Q outputs are enabled; when HIGH, all Q outputs are placed in the high-impedance state. Does not affect the internal latch state.
2 1Q tri_state Latch 1 3-state output. Follows 1D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
3 1D input Latch 1 data input. Data is transferred to the 1Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
4 2D input Latch 2 data input. Data is transferred to the 2Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
5 2Q tri_state Latch 2 3-state output. Follows 2D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
6 3Q tri_state Latch 3 3-state output. Follows 3D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
7 3D input Latch 3 data input. Data is transferred to the 3Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
8 4D input Latch 4 data input. Data is transferred to the 4Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
9 4Q tri_state Latch 4 3-state output. Follows 4D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
10 GND power_in Ground reference (0 V). Connect to system ground.
11 LE input Latch Enable input. When HIGH, the latch is transparent and Q outputs follow D inputs; on the HIGH-to-LOW transition, data is latched. Independent of OE.
12 5Q tri_state Latch 5 3-state output. Follows 5D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
13 5D input Latch 5 data input. Data is transferred to the 5Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
14 6D input Latch 6 data input. Data is transferred to the 6Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
15 6Q tri_state Latch 6 3-state output. Follows 6D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
16 7Q tri_state Latch 7 3-state output. Follows 7D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
17 7D input Latch 7 data input. Data is transferred to the 7Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
18 8D input Latch 8 data input. Data is transferred to the 8Q output while LE is HIGH and latched on the HIGH-to-LOW transition of LE.
19 8Q tri_state Latch 8 3-state output. Follows 8D when LE is HIGH, holds last value when LE is LOW, high-impedance when OE is HIGH.
20 VCC power_in Positive supply voltage, 4.5 V to 5.5 V (recommended operating range for HCT family). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

  • SN74HCT373PWR
  • SN74HCT373PWRDWR
  • SN74HCT373PWRDW
  • SN74HCT373PWRNSR
  • SN74HCT373PWRN

CAD (KiCad official)

  • Symbol: SN74HCT373PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 89e794fd27210daa, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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Datasheet

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