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SN74AHCT273PWR
Public Made by Adomby adom
Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownSN74AHCT273PWR
Texas Instruments · Logic ICs · TSSOP-20
SN74AHCT273PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active clear input (CLR) that acts as a direct clear on the octal D-type flip-flops; the datasheet lists it as a direct clear input. |
| 2 | 1Q | output | Output Q of flip-flop 1 (single-rail output). |
| 3 | 1D | input | Individual data input to flip-flop 1; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 4 | 2D | input | Individual data input to flip-flop 2; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 5 | 2Q | output | Output Q of flip-flop 2 (single-rail output). |
| 6 | 3Q | output | Output Q of flip-flop 3 (single-rail output). |
| 7 | 3D | input | Individual data input to flip-flop 3; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 8 | 4D | input | Individual data input to flip-flop 4; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 9 | 4Q | output | Output Q of flip-flop 4 (single-rail output). |
| 10 | GND | power_in | Ground pin. |
| 11 | CLK | input | Clock input; the flip-flops are positive-edge-triggered. |
| 12 | 5Q | output | Output Q of flip-flop 5 (single-rail output). |
| 13 | 5D | input | Individual data input to flip-flop 5; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 14 | 6D | input | Individual data input to flip-flop 6; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 15 | 6Q | output | Output Q of flip-flop 6 (single-rail output). |
| 16 | 7Q | output | Output Q of flip-flop 7 (single-rail output). |
| 17 | 7D | input | Individual data input to flip-flop 7; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 18 | 8D | input | Individual data input to flip-flop 8; inputs are TTL-voltage compatible and unused inputs must be held at VCC or GND. |
| 19 | 8Q | output | Output Q of flip-flop 8 (single-rail output). |
| 20 | VCC | power_in | Power supply pin; recommended supply range is 4.5 V to 5.5 V and absolute maximum is 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| VI Input voltage range | VI | -0.5 | 7 | V | 4 | ||
| VO Output voltage range | VO | -0.5 | V | max printed as VCC + 0.5 V | 4 | ||
| Input clamp current | IIK | -20 | mA | VI < 0 | 4 | ||
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -75 | 75 | mA | 4 | |||
| VCC Supply voltage | VCC | 4.5 | 5.5 | V | 4 | ||
| VIH High-level input voltage | VIH | 2 | V | 4 | |||
| VIL Low-level input voltage | VIL | 0.8 | V | 4 | |||
| VI Input voltage | VI | 0 | 5.5 | V | 4 | ||
| VO Output voltage | VO | 0 | V | max = VCC | 4 | ||
| High-level output current | IOH | -8 | mA | 4 | |||
| Low-level output current | IOL | 8 | mA | 4 | |||
| Input transition rise or fall rate | Δt/Δv | 20 | ns/V | 4 | |||
| Operating free-air temperature | TA | -40 | 125 | °C | 4 | ||
| VOH High-level output voltage | VOH | 4.4 | 4.5 | V | IOH = -50 µA; VCC = 4.5 V; TA = 25°C | 5 | |
| VOH High-level output voltage | VOH | 4.4 | V | IOH = -50 µA; VCC = 4.5 V; full operating temperature range | 5 | ||
| VOH High-level output voltage | VOH | 3.94 | V | IOH = -8 mA; VCC = 4.5 V; TA = 25°C | 5 | ||
| VOH High-level output voltage | VOH | 3.8 | V | IOH = -8 mA; VCC = 4.5 V; full operating temperature range | 5 | ||
| VOL Low-level output voltage | VOL | 0.1 | V | IOL = 50 µA; VCC = 4.5 V; TA = 25°C | 5 | ||
| VOL Low-level output voltage | VOL | 0.36 | V | IOL = 8 mA; VCC = 4.5 V; TA = 25°C | 5 | ||
| VOL Low-level output voltage | VOL | 0.44 | V | IOL = 8 mA; VCC = 4.5 V; full operating temperature range | 5 | ||
| Input current | II | -0.1 | 0.1 | µA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; TA = 25°C | 5 | |
| Input current | II | -1 | 1 | µA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; full operating temperature range | 5 | |
| Supply current | ICC | 40 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V; full operating temperature range | 5 | ||
| Increase in supply current per input | ΔICC | 1.5 | mA | One input at 3.4 V, other inputs at VCC or GND; VCC = 5.5 V; full operating temperature range | 5 | ||
| Input capacitance | Ci | 2.5 | 10 | pF | VI = VCC or GND; VCC = 5 V; TA = 25°C | 5 | |
| Input capacitance | Ci | 10 | pF | VI = VCC or GND; VCC = 5 V; full operating temperature range | 5 | ||
| Pulse duration, CLR low | tw | 5 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 5 | ||
| Pulse duration, CLR low | tw | 6 | ns | VCC = 5 V ± 0.5 V; full operating temperature range | 5 | ||
| Pulse duration, CLK high or low | tw | 5 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 5 | ||
| Pulse duration, CLK high or low | tw | 6.5 | ns | VCC = 5 V ± 0.5 V; full operating temperature range | 5 | ||
| Setup time, data before CLK↑ | tsu | 5 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 5 | ||
| Setup time, CLR before CLK↑ | tsu | 2.5 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 5 | ||
| Hold time, data after CLK↑ | th | 0 | ns | VCC = 5 V ± 0.5 V; TA = 25°C | 5 | ||
| Maximum clock frequency | fmax | 75 | 120 | MHz | CL = 15 pF; TA = 25°C | 6 | |
| Maximum clock frequency | fmax | 65 | MHz | CL = 15 pF; full operating temperature range | 6 | ||
| Maximum clock frequency | fmax | 50 | 75 | MHz | CL = 50 pF; TA = 25°C | 6 | |
| Maximum clock frequency | fmax | 45 | MHz | CL = 50 pF; full operating temperature range | 6 | ||
| Propagation delay CLR to Q (tPHL) | tPHL | 7.5 | 10 | ns | CL = 15 pF; TA = 25°C | 6 | |
| Propagation delay CLR to Q (tPHL) | tPHL | 1 | 11.6 | ns | CL = 15 pF; full operating temperature range | 6 | |
| Propagation delay CLK to Q (tPLH) | tPLH | 5.5 | 7.5 | ns | CL = 15 pF; TA = 25°C | 6 | |
| Propagation delay CLK to Q (tPLH) | tPLH | 1 | 8.8 | ns | CL = 15 pF; full operating temperature range | 6 | |
| Propagation delay CLK to Q (tPHL) | tPHL | 5.8 | 8.2 | ns | CL = 15 pF; TA = 25°C | 6 | |
| Propagation delay CLK to Q (tPHL) | tPHL | 1 | 10 | ns | CL = 15 pF; full operating temperature range | 6 | |
| Propagation delay CLR to Q (tPHL) | tPHL | 8.5 | 11 | ns | CL = 50 pF; TA = 25°C | 6 | |
| Propagation delay CLR to Q (tPHL) | tPHL | 1 | 12.6 | ns | CL = 50 pF; full operating temperature range | 6 | |
| Propagation delay CLK to Q (tPLH) | tPLH | 6.5 | 8.5 | ns | CL = 50 pF; TA = 25°C | 6 | |
| Propagation delay CLK to Q (tPLH) | tPLH | 1 | 9.8 | ns | CL = 50 pF; full operating temperature range | 6 | |
| Propagation delay CLK to Q (tPHL) | tPHL | 6.8 | 9.2 | ns | CL = 50 pF; TA = 25°C | 6 | |
| Propagation delay CLK to Q (tPHL) | tPHL | 1 | 11 | ns | CL = 50 pF; full operating temperature range | 6 | |
| Junction-to-ambient thermal resistance (PW, TSSOP) | RθJA | 116.8 | °C/W | PW (TSSOP) package, 20 pins | 5 | ||
| Junction-to-case (top) thermal resistance (PW, TSSOP) | RθJC(top) | 58.5 | °C/W | PW (TSSOP) package, 20 pins | 5 | ||
| Junction-to-board thermal resistance (PW, TSSOP) | RθJB | 78.7 | °C/W | PW (TSSOP) package, 20 pins | 5 |
CAD (KiCad official)
- Symbol:
SN74AHCT273PWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ahct273pwr-etched.step/sn74ahct273pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahct273pwr.step/sn74ahct273pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
7aa6080baa507875, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).