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MSP430FR2110IPW16R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2110IPW16R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-16
MSP430FR2110IPW16R from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1/UCA0CLK/ACLK/C1/A1 | bidirectional | Port 1.1 general I/O; alternates to UCA0CLK SPI clock, ACLK auxiliary clock output, C1 comparator input, or A1 ADC analog input; reset state high impedance. |
| 2 | P1.0/UCA0STE/SMCLK/C0/A0/Veref+ | bidirectional | Port 1.0 general I/O; alternates to UCA0STE SPI slave enable, SMCLK submain clock output, C0 comparator input, A0 ADC analog input, or Veref+ ADC positive reference input; reset state high impedance. |
| 3 | TEST/SBWTCK | input | Test mode selection pin with internal pulldown; alternates to SBWTCK Spy-Bi-Wire protocol clock input; always disabled as general I/O. |
| 4 | RST/NMI/SBWTDIO | bidirectional | Reset input (active low) or configurable as NMI non-maskable interrupt input; serves as SBWTDIO Spy-Bi-Wire data bidirectional pin in debug mode; 47kΩ external pullup or 10nF internal/external pulldown required per section 7.5. |
| 5 | DVCC | power_in | Digital power supply voltage input 1.8V to 3.6V with 4.7µF to 10µF bypass capacitor and 100nF low-ESR ceramic capacitor recommended per section 8.3. |
| 6 | DVSS | power_in | Digital power supply ground; provides return path for all digital circuits and substrate connection. |
| 7 | P2.7/TB0CLK/XIN | bidirectional | Port 2.7 general I/O with interrupt capability (LPM wake); alternates to TB0CLK Timer_B0 external clock input or XIN 32kHz crystal oscillator input; reset state high impedance. |
| 8 | P2.6/MCLK/XOUT | bidirectional | Port 2.6 general I/O with interrupt capability (LPM wake); alternates to MCLK main clock output or XOUT 32kHz crystal oscillator output; reset state high impedance. |
| 9 | P2.1/TB0.2 | bidirectional | Port 2.1 general I/O with interrupt capability (LPM wake); alternates to Timer_B0 CCR2 capture input or compare/PWM output TB0.2; reset state high impedance. |
| 10 | P2.0/TB0.1/COUT | bidirectional | Port 2.0 general I/O with interrupt capability (LPM wake); alternates to Timer_B0 CCR1 capture input or compare/PWM output TB0.1, or eCOMP0 comparator output COUT; reset state high impedance. |
| 11 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+ | bidirectional | Port 1.7 general I/O; alternates to UCA0TXD UART transmit, UCA0SIMO SPI slave input/master output, TB0.2 Timer_B0 CCR2, JTAG TDO output, A7 ADC analog input, or VREF+ 1.2V reference output (1.158-1.242V, 30µV/°C typical); disabled during JTAG debug. |
| 12 | P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6 | bidirectional | Port 1.6 general I/O; alternates to UCA0RXD UART receive, UCA0SOMI SPI slave output/master input, TB0.1 Timer_B0 CCR1, JTAG TDI/TCLK debug interface, or A6 ADC analog input; disabled during JTAG debug. |
| 13 | P1.5/UCA0CLK/TMS/A5 | bidirectional | Port 1.5 general I/O; alternates to UCA0CLK SPI clock, JTAG TMS test mode select, or A5 ADC analog input; disabled during JTAG debug. |
| 14 | P1.4/UCA0STE/TCK/A4 | bidirectional | Port 1.4 general I/O; alternates to UCA0STE SPI slave enable, JTAG TCK test clock input, or A4 ADC analog input; disabled during JTAG debug. |
| 15 | P1.3/UCA0TXD/UCA0SIMO/C3/A3 | bidirectional | Port 1.3 general I/O; alternates to UCA0TXD UART transmit, UCA0SIMO SPI slave input/master output, C3 comparator input, or A3 ADC analog input; reset state high impedance. |
| 16 | P1.2/UCA0RXD/UCA0SOMI/TB0TRG/C2/A2/Veref- | bidirectional | Port 1.2 general I/O; alternates to UCA0RXD UART receive, UCA0SOMI SPI slave output/master input, TB0TRG Timer_B0 external trigger, C2 comparator input, A2 ADC analog input, or Veref- ADC negative reference input; reset state high impedance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Embedded Processors & Controllers |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
MSP430FR2110IPW16R - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
msp430fr2110ipw16r-etched.step/msp430fr2110ipw16r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2110ipw16r.step/msp430fr2110ipw16r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (87 pp, sha256
7505f67fee2c23fa, retrieved 2026-09-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).