AD5665RBRUZ-1 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LDAC	input	Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, or it can be tied permanently low.
2	ADDR1	input	Three-state address input that sets the two least significant bits (A1, A0) of the 7-bit slave address.
3	VDD	power_in	Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4	VOUTA	output	Analog output voltage from DAC A, with a rail-to-rail output amplifier.
5	VOUTC	output	Analog output voltage from DAC C, with a rail-to-rail output amplifier.
6	POR	input	Power-on reset pin: tying it to GND powers up the device to 0 V, and tying it to VDD powers up the device to midscale.
7	VREFIN/VREFOUT	bidirectional	Reference input by default when using an external reference, or reference output when using the internal 2.5 V reference (R suffix versions only).
8	ADDR2	input	Three-state address input that sets bits A3 and A2 of the 7-bit slave address.
9	CLR	input	Falling-edge sensitive asynchronous clear input that, while low, ignores all LDAC pulses and, when activated, loads zero scale to all input and DAC registers and clears the output to 0 V.
10	VOUTD	output	Analog output voltage from DAC D, with a rail-to-rail output amplifier.
11	VOUTB	output	Analog output voltage from DAC B, with a rail-to-rail output amplifier.
12	GND	power_in	Ground reference point for all circuitry on the device.
13	SDA	bidirectional	Bidirectional open-drain serial data line, used with SCL to clock data into or out of the 16-bit input register, that should be pulled to the supply with an external pull-up resistor.
14	SCL	input	Serial clock line used with SDA to clock data into or out of the 16-bit input register.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-14
Category	Communication Interface Chip/UART/485/232
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD	VDD	2.7		5.5	V		4
Normal mode supply current, internal reference off	IDD		1	1.16	mA	VIH = VDD, VIL = GND, full-scale loaded; VDD = 4.5 V to 5.5 V; internal reference off	4
Normal mode supply current, internal reference off	IDD		0.9	1.05	mA	VIH = VDD, VIL = GND, full-scale loaded; VDD = 2.7 V to 3.6 V; internal reference off	4
Normal mode supply current, internal reference on	IDD		1.9	2.14	mA	VIH = VDD, VIL = GND, full-scale loaded; VDD = 4.5 V to 5.5 V; internal reference on	4
Normal mode supply current, internal reference on	IDD		1.4	1.59	mA	VIH = VDD, VIL = GND, full-scale loaded; VDD = 2.7 V to 3.6 V; internal reference on	4
All power-down modes supply current (TSSOP)	IDD		0.48	1	µA	VIH = VDD, VIL = GND; VDD = 3.6 V to 5.5 V (TSSOP)	4
Relative accuracy (INL)		-16	8	16	LSB		3
Differential nonlinearity		-1		1	LSB	Guaranteed monotonic by design	3
Zero-code error			2	10	mV	All 0s loaded to DAC register	3
Offset error		-10	1	10	mV		3
Full-scale error		-0.5	-0.1	0.5	% FSR	All 1s loaded to DAC register	3
Gain error		-1	0.1	1	% FSR		3
Zero-code error drift		-2		2	µV/°C		3
Gain temperature coefficient		-2.5		2.5	ppm Of FSR/°C		3
Reference current			210	260	µA	VREF = VDD = 5.5 V	3
Output voltage range, internal reference disabled		0			V	Internal reference disabled (printed maximum is VDD)	3
Output voltage range, internal reference enabled		0			V	Internal reference enabled (printed maximum is 2 × VREF)	3
Reference output voltage (2.5 V)		2.495		2.505	V	VDD = 4.5 V to 5.5 V; At ambient	4
Reference temperature coefficient (2.5 V)		-5		5	ppm/°C	VDD = 4.5 V to 5.5 V	4
Logic input current (ADDRx, CLR, LDAC, POR)	IIN	-1		1	µA		4
Logic input current (SDA, SCL)	IIN	-1		1	µA		4
Logic output low voltage (SDA)	VOL			0.4	V	ISINK = 3 mA	4
Logic output low voltage (SDA)	VOL			0.6	V	ISINK = 6 mA	4
Floating-state leakage current (SDA)		-1		1	µA		4
SDA data hold time	t4	0		3.45	µs	Standard mode	8
SDA data hold time	t4	0		0.9	µs	Fast mode	8
Pulse width of suppressed spike	tSP	0		50	ns	Fast mode	8
Output voltage settling time (¼ to ¾ scale)			4	7	µs	¼ to ¾ scale settling to ±2 LSB	7
VDD to GND	VDD	-0.3		7	V		10
VOUT to GND	VOUT	-0.3			V	Printed maximum is VDD + 0.3 V	10
VREFIN/VREFOUT to GND		-0.3			V	Printed maximum is VDD + 0.3 V	10
Digital input voltage to GND		-0.3			V	Printed maximum is VDD + 0.3 V	10
Operating temperature range, industrial		-40		105	°C		10
Storage temperature range		-65		150	°C		10
Junction temperature (TJ maximum)	TJ			150	°C		10
Reflow soldering peak temperature, RoHS compliant			260		°C	Printed as 260°C ± 5°C	10
Thermal impedance, junction-to-ambient, TSSOP	θJA		150.4		°C/W	TSSOP package	10

CAD (KiCad official)

Symbol: AD5665RBRUZ-1
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: ad5665rbruz-1-etched.step / ad5665rbruz-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5665rbruz-1.step / ad5665rbruz-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (35 pp, sha256 92ae60d05500e362, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5665RBRUZ-1

Verified AD5665RBRUZ-1

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3D Model

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Datasheet

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