component
TPS62153AQRGTRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS62153AQRGTRQ1
Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)
TPS62153AQRGTRQ1 from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switch node connected to the internal MOSFET switches; the inductor connects between SW and the output capacitor. |
| 2 | SW | output | Switch node connected to the internal MOSFET switches; the inductor connects between SW and the output capacitor. |
| 3 | SW | output | Switch node connected to the internal MOSFET switches; the inductor connects between SW and the output capacitor. |
| 4 | PG | output | Open-drain power-good output: High = VOUT ready, Low = VOUT below nominal regulation; requires a pull-up resistor. |
| 5 | FB | input | Voltage feedback input of the adjustable version; connect the resistive divider to this pin, and connect it to AGND on fixed-output versions for improved thermal performance. |
| 6 | AGND | power_in | Analog ground; must be connected directly to the Exposed Thermal Pad and the common ground plane. |
| 7 | FSW | input | Switching frequency select: Low = 2.5 MHz, High = 1.25 MHz for typical operation; an internal pull-down keeps the logic level low if the pin is floating. |
| 8 | DEF | input | Output voltage scaling: Low = nominal output voltage, High = nominal + 5%; an internal pull-down keeps the logic level low if the pin is floating. |
| 9 | SS/TR | input | Soft-start and tracking pin; an external capacitor on this pin sets the internal voltage reference rise time, and it can be used for tracking and sequencing. |
| 10 | AVIN | power_in | Supply voltage for the control circuitry; connect to the same source as PVIN, within the 3 V to 17 V recommended supply range. |
| 11 | PVIN | power_in | Supply voltage for the power stage; connect to the same source as AVIN, within the 3 V to 17 V recommended supply range. |
| 12 | PVIN | power_in | Supply voltage for the power stage; connect to the same source as AVIN, within the 3 V to 17 V recommended supply range. |
| 13 | EN | input | Enable input: High = enabled, Low = disabled; an internal pull-down keeps the logic level low if the pin is floating. |
| 14 | VOS | input | Output voltage sense pin and connection for the control loop circuitry. |
| 15 | PGND | power_in | Power ground; must be connected directly to the Exposed Thermal Pad and the common ground plane. |
| 16 | PGND | power_in | Power ground; must be connected directly to the Exposed Thermal Pad and the common ground plane. |
| 17 | EP (Exposed Thermal Pad) | power_in | Exposed thermal pad; must be connected to AGND (pin 6), PGND (pins 15, 16) and the common ground plane, and soldered for appropriate power dissipation and mechanical reliability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage, VIN (at AVIN and PVIN) | VIN | 3 | 17 | V | 4 | ||
| Operating junction temperature, TJ | TJ | -40 | 125 | °C | 4 | ||
| Input voltage range | VIN | 3 | 17 | V | 5 | ||
| Pin voltage AVIN, PVIN | -0.3 | 20 | V | 4 | |||
| Pin voltage EN, SS/TR, SW (DC) | -0.3 | V | 4 | ||||
| Pin voltage SW (AC), less than 10ns | -2 | 24.5 | V | less than 10ns | 4 | ||
| Pin voltage DEF, FSW, FB, PG, VOS | -0.3 | 7 | V | 4 | |||
| Power Good sink current PG | 10 | mA | 4 | ||||
| Operating junction temperature range, TJ | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature range, Tstg | Tstg | -65 | 150 | °C | 4 | ||
| Electrostatic discharge, human body model (HBM) | V(ESD) | -2000 | 2000 | V | Human body model (HBM), per AEC Q100-002 | 4 | |
| Electrostatic discharge, charged device model (CDM) | V(ESD) | -500 | 500 | V | Charged device model (CDM), per AEC Q100-011 | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 45 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 53.6 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 17.4 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 1.1 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ψJB | 17.4 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 4.5 | °C/W | 4 | |||
| Operating quiescent current | IQ | 17 | 30 | µA | EN=High, IOUT=0mA, device not switching | 5 | |
| Shutdown current | ISD | 1.5 | 25 | µA | EN=Low | 5 | |
| Undervoltage lockout threshold | VUVLO | 2.6 | 2.7 | 2.8 | V | Falling Input Voltage (PWM mode operation) | 5 |
| Undervoltage lockout hysteresis | 200 | mV | 5 | ||||
| Thermal shutdown temperature | TSD | 160 | °C | 5 | |||
| Thermal shutdown hysteresis | 20 | °C | 5 | ||||
| High level input threshold voltage (EN, DEF, FSW) | VH | 0.9 | V | 5 | |||
| Low level input threshold voltage (EN, DEF, FSW) | VL | 0.3 | V | 5 | |||
| Input leakage current (EN, DEF, FSW) | ILKG | 0.01 | 1 | µA | EN=VIN or GND; DEF=VOUT or GND; FSW=GND | 5 | |
| Power good threshold voltage, rising | VTH_PG | 92 | 95 | 98 | %VOUT | Rising (%VOUT) | 5 |
| Power good threshold voltage, falling | VTH_PG | 87 | 90 | 94 | %VOUT | Falling (%VOUT) | 5 |
| Power good output low | VOL_PG | 0.07 | 0.3 | V | IPG=–2mA | 5 | |
| Input leakage current (PG) | ILKG_PG | 1 | 400 | nA | VPG=1.8V | 5 | |
| SS/TR pin source current | ISS/TR | 2.3 | 2.5 | 2.7 | µA | 5 | |
| High-side MOSFET ON-resistance | RDS(ON) | 90 | 170 | mΩ | VIN≥6V | 5 | |
| High-side MOSFET ON-resistance | RDS(ON) | 120 | mΩ | VIN=3V | 5 | ||
| Low-side MOSFET ON-resistance | RDS(ON) | 40 | 70 | mΩ | VIN≥6V | 5 | |
| Low-side MOSFET ON-resistance | RDS(ON) | 50 | mΩ | VIN=3V | 5 | ||
| High-side MOSFET forward current limit | ILIMF | 1.4 | 1.7 | 2.2 | A | VIN =12V, TA= 25°C | 5 |
| Internal reference voltage | VREF | 0.8 | V | 5 | |||
| Input leakage current (FB) | ILKG_FB | 1 | 100 | nA | VFB=0.8V | 5 | |
| Output voltage accuracy (PWM mode) | -1.8 | 1.8 | % | PWM mode operation, VIN ≥ VOUT +1V | 5 | ||
| Output voltage accuracy (Power Save Mode) | -2.3 | 2.8 | % | Power Save Mode operation, COUT=22µF | 5 | ||
| Load regulation | 0.05 | %/A | VIN=12V, VOUT=3.3V, PWM mode operation | 5 | |||
| Line regulation | 0.02 | %/V | 3V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 1A, PWM mode operation | 5 |
CAD (KiCad official)
- Symbol:
TPS62153AQRGTRQ1 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps62153aqrgtrq1-etched.step/tps62153aqrgtrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps62153aqrgtrq1.step/tps62153aqrgtrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
e6f7e40302057bc1, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).