component
MP9928GL-Z
Public Made by Adomby adom
Monolithic Power Systems MPS Global Sourcing Parts, QFN-20(3x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMP9928GL-Z
Monolithic Power Systems MPS · Global Sourcing Parts · QFN-20(3x4)
MP9928GL-Z from Monolithic Power Systems MPS, in a QFN-20(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC2 | power_in | External supply input for the internal VCC1 regulator; it disables the VIN-powered regulator when above 4.7V and must not exceed 12V. |
| 2 | VCC1 | power_out | Internal bias supply output that needs a 1µF or greater ceramic decoupling capacitor, with no more than 4.7µF. |
| 3 | SGND | power_in | Low-noise signal ground reference for the controller. |
| 4 | SS | input | Soft-start control input, where an external capacitor from SS to SGND sets the soft-start period using the 4µA charge current. |
| 5 | COMP | passive | Error amplifier compensation node, where an RC network from COMP to GND compensates the regulation loop. |
| 6 | FB | input | Feedback input to the error amplifier, where the output divider to GND is compared to the internal 0.8V reference. |
| 7 | CCM/AAM | input | Mode select pin: tied to VCC1 or floating selects CCM, while a resistor to GND sets AAM with VAAM no less than 480mV. |
| 8 | FREQ | passive | A resistor between FREQ and GND sets the switching frequency. |
| 9 | PG | output | Open-drain power-good output that is pulled low when the output is outside about ±10% of nominal and should be pulled up to no more than 5V through a resistor. |
| 10 | ILIM | input | Current-sense limit select with three fixed settings: GND gives 25mV, VCC1 gives 50mV, and floating gives 75mV. |
| 11 | SYNCO | output | Outputs a clock 180° out of phase with the internal or external sync clock in CCM or DCM (not Sleep mode) for dual-channel co-pack, and a DC voltage in other modes. |
| 12 | SENSE- | input | Negative input for current sensing, with the limit threshold set by the ILIM pin. |
| 13 | SENSE+ | input | Positive input for current sensing, with the limit threshold set by the ILIM pin. |
| 14 | PGND | power_in | Power ground for the internal low-side driver and VCC1 regulator, to be connected directly to the negative terminal of the VCC1 decoupling capacitor. |
| 15 | BG | output | Bottom gate driver output that connects to the gate of the synchronous N-channel MOSFET. |
| 16 | SW | passive | Switch node that serves as the reference for the VBST supply and the high-current return for the bootstrapped switch. |
| 17 | TG | output | Top gate drive output for the top N-channel MOSFET, driven from the BST capacitor and returned to SW. |
| 18 | BST | power_in | Bootstrap positive supply for the floating high-side driver, with a bypass capacitor to SW and a diode from VCC1 charging it. |
| 19 | IN | power_in | Input supply for the 4V to 60V operating range, with a ceramic capacitor needed to prevent large voltage spikes at the input. |
| 20 | EN/SYNC | input | Enable input with 1.22V rising threshold and 130mV hysteresis, which also accepts an external sync clock that the internal oscillator follows. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems MPS |
| Package | QFN-20(3x4) |
| Category | Global Sourcing Parts |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VIN) | VIN | 4 | 60 | V | 3 | ||
| Output voltage (VOUT) | VOUT | 24 | V | 3 | |||
| Supply voltage for (VCC2) | VCC2 | 5 | 12 | V | 3 | ||
| Operating junction temperature (TJ) | TJ | -40 | 125 | °C | 3 | ||
| Input supply voltage (VIN) | VIN | -0.3 | 65 | V | 3 | ||
| EN/SYNC | EN/SYNC | -0.3 | 50 | V | 3 | ||
| SW | SW | -0.3 | 65 | V | -4V for <20ns | 3 | |
| BST - SW | BST-SW | -0.3 | 6.5 | V | 3 | ||
| Supply voltage (VCC1) | VCC1 | -0.3 | 6.5 | V | 3 | ||
| External supply voltage (VCC2) | VCC2 | -0.3 | 15 | V | 3 | ||
| SENSE + / - | SENSE+/- | -0.3 | 28 | V | 3 | ||
| Differential sense (SENSE+ to SENSE-) | SENSE+ to SENSE- | -0.7 | 0.7 | V | 3 | ||
| All other pins | -0.3 | 6.5 | V | 3 | |||
| Continuous power dissipation, QFN-20 (3mmx4mm) | PD | 2.6 | W | TA = +25°C | 3 | ||
| Lead temperature | 260 | °C | 3 | ||||
| Storage temperature | TSTG | -65 | 175 | °C | 3 | ||
| VIN UVLO threshold (rising) | INUV_RISING | 4.5 | 5 | V | 4 | ||
| VIN UVLO threshold (falling) | INUV_FALLING | 3.7 | 3.95 | V | 4 | ||
| VIN supply current with VCC2 bias | IQ_VCC2 | 25 | 40 | μA | VCC2 = 12V, external bias | 4 | |
| VIN supply current without VCC2 bias | IQ | 750 | 1000 | μA | VCC2 = 0, VFB = 0.84V, VAAM = 5V, SENSE+ = SENSE- = 0.3V | 4 | |
| VIN AAM current | IQ_AAM | 250 | 350 | μA | VAAM=0.6V, VFB=0.84V, SENSE+ = SENSE- = 0.3V | 4 | |
| VIN shutdown current | ISHDN | 0.5 | 3 | μA | VEN = 0V | 4 | |
| VCC1 regulator load regulation from VIN | 1 | 3 | % | Load = 0 to 50mA, VCC2 floating or connects to GND | 4 | ||
| VCC1 regulator load regulation from VCC2 | 1 | 3 | % | Load = 0 to 50mA, VCC2 = 12V | 4 | ||
| VCC2 UVLO threshold (rising) | VCC2_RISING | 4.7 | 4.92 | V | 4 | ||
| VCC2 supply current (VAAM = 5V) | IVCC2 | 800 | 1200 | μA | VAAM = 5V, VFB = 0.84V, VCC2 = 12V | 4 | |
| VCC2 supply current (VAAM = 0.6V) | IVCC2 | 200 | 300 | μA | VAAM = 0.6V, VFB = 0.84V, VCC2 = 12V | 4 | |
| Feedback voltage (TJ = 25°C) | VFB | 0.792 | 0.8 | 0.808 | V | 4V ≤ VIN ≤ 60V, TJ=25C | 4 |
| Feedback voltage (TJ = -40°C to 125°C) | VFB | 0.788 | 0.8 | 0.812 | V | 4V ≤ VIN ≤ 60V, TJ=-40C to 125C | 4 |
| Enable threshold (rising) | VEN_RISING | 1.16 | 1.22 | 1.28 | V | 4 | |
| Enable threshold (falling) | VEN_FALLING | 1.03 | 1.09 | 1.15 | V | 4 | |
| Enable turn-off delay | TOFF | 10 | 15 | μs | 4 | ||
| Operating frequency | FSW | 240 | 300 | 360 | kHz | R Freq = 65kΩ | 5 |
| Maximum programmable frequency | FSWH | 1000 | kHz | 5 | |||
| Minimum programmable frequency | FSWL | 100 | kHz | 5 | |||
| Sync/EN frequency range | FSYNC | 100 | 1000 | kHz | 5 | ||
| Current sense common mode voltage range | VSENSE+/- | 0 | 24 | V | 5 | ||
| Current limit sense voltage (ILIM = GND) | VILIMIT | 15 | 25 | 35 | mV | ILIM = GND, VSENSE+ = 3.3V | 5 |
| Current limit sense voltage (ILIM = VCC1) | VILIMIT | 40 | 50 | 60 | mV | ILIM = VCC1, VSENSE+ = 3.3V | 5 |
| Current limit sense voltage (ILIM = FLOAT) | VILIMIT | 65 | 75 | 85 | mV | ILIM = FLOAT, VSENSE+ = 3.3V | 5 |
| Soft-start source current | ISS | 2 | 4 | 6 | μA | SS = 0.5V | 5 |
| Error amp sink/source current | IEA | -30 | 30 | μA | FB = 0.7/0.9V | 5 | |
| Over-voltage threshold | VOV | 110 | 115 | 120 | % VFB | 5 | |
| TG maximum duty cycle | Dmax | 98 | 99.5 | % | VFB = 0.7V | 6 | |
| BG minimum on time | TON_MIN_BG | 175 | 250 | ns | 6 | ||
| Power good low | VPG_Low | 0.1 | 0.3 | V | ISINK = 4mA | 6 | |
| PG rising threshold (VOUT rising) | PGVth_RSING | 85 | 90 | 96.5 | % VFB | VOUT rising | 6 |
| PG rising threshold (VOUT falling) | PGVth_RSING | 101 | 107 | 112.5 | % VFB | VOUT falling | 6 |
| PG falling threshold (VOUT falling) | PGVth_FALLING | 81 | 87 | 92.5 | % VFB | VOUT falling | 6 |
| PG falling threshold (VOUT rising) | PGVth_FALLING | 105 | 110 | 116.5 | % VFB | VOUT rising | 6 |
| Thermal resistance junction-to-ambient, QFN-20 (3mmx4mm) | θJA | 48 | C/W | JESD51-7, 4-layer PCB | 3 | ||
| Thermal resistance junction-to-case, QFN-20 (3mmx4mm) | θJC | 10 | C/W | JESD51-7, 4-layer PCB | 3 |
CAD (KiCad official)
- Symbol:
MP9928GL-Z - Footprint:
Package_DFN_QFN:QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm - 3D model: QFN-20(3x4) (KiCad packages3D, STEP)
- 3D model files:
mp9928gl-z-etched.step/mp9928gl-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp9928gl-z.step/mp9928gl-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems MPS datasheet (25 pp, sha256
61fba8c327700363, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).