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MAX17261METD+

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Analog Devices Inc Maxim Integrated Battery Management, TDFN-14(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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MAX17261METD+

Analog Devices Inc Maxim Integrated · Battery Management · TDFN-14(3x3)

MAX17261METD+ from Analog Devices Inc Maxim Integrated, in a TDFN-14(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TH input Thermistor input: connect a thermistor from TH to GND; TH also provides battery insertion/removal detection, and should be connected to BATT if not used.
2 NC unconnected No Connection.
3 SW output Gate switch signal used to control an optional FET in the resistor divider circuit for low-power operation.
4 NC unconnected No Connection.
5 NC unconnected No Connection.
6 BATT power_in IC power supply: connect to a 3 to 5 volt supply and bypass with a 0.1µF capacitor to GND.
7 CSN input Sense resistor negative sense point, Kelvin connected to the system side of the sense resistor.
8 GND power_in IC ground.
9 CSPL input Sense resistor positive sense point, Kelvin connected to the cell side of the sense resistor.
10 CELLX input Voltage measurement point for multiple-series cell applications, connected to an external voltage divider to measure a fraction of the cell voltage.
11 REG power_out Internal 1.8V regulator output: bypass with an external 0.47µF capacitor to GND and do not load externally.
12 ALRT output Open-drain active-low alert output indicating fuel-gauge alerts; connect to GND if not used.
13 SDA bidirectional Serial data input/output of the 2-wire I2C interface; open-drain output driver with an internal pulldown for disconnection sensing.
14 SCL input Serial clock input of the 2-wire I2C interface; input only, with an internal pulldown for disconnection sensing.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package TDFN-14(3x3)
Category Power Management (PMIC)
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Shutdown Supply Current IDD0 0.5 0.9 μA TA ≤ +50ºC 7
Hibernate Supply Current IDD1 5.1 12 μA TA ≤ +50ºC, average current 7
Active Supply Current IDD2 15 30 μA TA ≤ +50ºC, average current not including thermistor measurement current 7
Supply Voltage VBATT 2.3 4.9 V 7
Regulation Voltage VREG 1.8 V 7
Startup Voltage VBATTSU 3 V 7
CELLX Measurement Error VXGERR -0.2 0.2 % of Reading TA = +25ºC 7
CELLX Measurement Error VXGERR -0.5 0.5 % of Reading -40ºC ≤ TA ≤ 85ºC 7
CELLX Measurement Range VXFS 0.92 2 V 7
Current Measurement Offset Error IOERR -1.5 1.5 μV Long-term average without load current 7
Current Measurement Error IGERR -1 1 % of Reading 7
Current Measurement Range IFS -51.2 51.2 mV 7
Internal Temperature Measurement Error TIGERR -1 1 ºC -40ºC ≤ TA ≤ +85ºC 7
External Thermistance Resistance (Config.R100 = 0) REXT10 10 kΩ Config.R100 = 0 7
External Thermistance Resistance (Config.R100 = 1) REXT100 100 kΩ Config.R100 = 1 7
Output Drive Low, ALRT, SDA VOL 0.4 V IOL = 4mA, VBATT = 2.3V 7
Input Logic High, ALRT, SCL, SDA VIH 1.5 V 7
Input Logic Low, ALRT, SCL, SDA VIL 0.5 V 7
Battery-Detach Detection Threshold VDET 91 96.2 99 % Measured as a fraction of VBATT on TH rising 7
Battery-Detach Detection Threshold Hysteresis VDET-HYS 1 % Measured as a fraction of VBATT on TH falling 8
Battery-Detach Comparator Delay tTOFF 100 μs TH step from 70% to 100% of VBATT (Alrtp = 0, EnAIN = 1, FTHRM = 1) 8
Leakage Current, CSN, ALRT ILEAK -1 1 μA VALRT < 15V 8
Leakage Current, CELLX ILEAK_CELLX -60 60 nA VCELLX < 2.0V 8
Input Pulldown Current IPD 0.05 0.2 0.4 μA VSDA = 0.4V, VSCL = 0.4V 8
SCL Clock Frequency fSCL 0 400 kHz Note 2 8
Bus Free Time Between a STOP and START Condition tBUF 1.3 μs 8
Hold Time (Repeated) START Condition tHD:STA 0.6 μs Note 3 8
Low Period of SCL Clock tLOW 1.3 μs 8
High Period of SCL Clock tHIGH 0.6 μs 8
Setup Time for a Repeated START Condition tSU:STA 0.6 μs 8
Data Hold Time tHD:DAT 0 0.9 μs Notes 4, 5 8
Data Setup Time tSU:DAT 100 ns Note 4 8
Rise Time of Both SDA and SCL Signals tR 5 300 ns 8
Fall Time of Both SDA and SCL Signals tF 5 300 ns 8
Setup Time for STOP Condition tSU:STO 0.6 μs 8
Spike Pulse Width Suppressed by Input Filter tSP 50 ns Note 6 8
Capacitive Load for Each Bus Line CB 400 pF Note 7 8
SCL, SDA Input Capacitance CBIN 6 pF 8
Time-Base Accuracy tERR -1 1 % TA = +25°C 8
TH Precharge Time tPRE 8.48 ms 9
BATT to GND -0.3 6 V 6
ALRT to GND -0.3 17 V 6
REG to GND -0.3 2.2 V 6
TH to GND -0.3 V 6
CELLX to GND -0.3 V 6
CSN to GND -0.3 V 6
CSPL to GND -0.3 0.3 V 6
SDA, SCL to GND -0.3 6 V 6
SW to GND -0.3 V 6
Operating Temperature Range -40 85 °C 6
Junction Temperature 150 °C 6
Storage Temperature Range -55 125 °C 6
Soldering Temperature (reflow) 260 °C 6
Continuous Source Current for TH 1 mA 6
Lead Temperature (soldering 10s) 300 ºC soldering 10s 6
Junction to Ambient, Single-Layer Board (TDFN) θJA 54 ºC/W JESD51-7, single-layer board 6
Junction to Case, TDFN θJC 8 ºC/W JESD51-7, single-layer board 6
Junction to Ambient, Four-Layer Board (TDFN) θJA 41 ºC/W JESD51-7, four-layer board 6
Junction to Case, TDFN (four-layer) θJC 8 ºC/W JESD51-7, four-layer board 6

CAD (KiCad official)

  • Symbol: MAX17261METD+
  • Footprint: Package_DFN_QFN:DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm
  • 3D model: TDFN-14(3x3) (KiCad packages3D, STEP)
  • 3D model files: max17261metd-etched.step / max17261metd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max17261metd.step / max17261metd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (32 pp, sha256 fb34c45047a3412b, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF