YT8531DH-CA from Motorcomm, in a QFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TRXP0	bidirectional	Media-dependent interface 0 positive; 100Ω differential MDI transmission line to magnetics/RJ45.
2	TRXN0	bidirectional	Media-dependent interface 0 negative; 100Ω differential MDI transmission line.
3	AVDDL	power_in	Analog core power supply, 1.1V/1.2V. Sourced from internal LDO2 output (LDO_O, pin 30) on YT8531DH.
4	TRXP1	bidirectional	Media-dependent interface 1 positive; 100Ω differential MDI transmission line.
5	TRXN1	bidirectional	Media-dependent interface 1 negative; 100Ω differential MDI transmission line.
6	TRXP2	bidirectional	Media-dependent interface 2 positive; 100Ω differential MDI transmission line.
7	TRXN2	bidirectional	Media-dependent interface 2 negative; 100Ω differential MDI transmission line.
8	AVDDL	power_in	Analog core power supply, 1.1V/1.2V. Second analog core-power pin; tie to same rail as pin 3.
9	TRXP3	bidirectional	Media-dependent interface 3 positive; 100Ω differential MDI transmission line.
10	TRXN3	bidirectional	Media-dependent interface 3 negative; 100Ω differential MDI transmission line.
11	AVDD33	power_in	Analog 3.3V power supply for the PHY analog front end.
12	RESET_N	input	Hardware reset, active low. Requires an external pull-up resistor (internal pull-up also present).
13	MDC	input	Management Data Clock (SMI/MDIO interface). Internal pull-down.
14	MDIO	bidirectional	Management data input/output (SMI). Internal pull-up. Must be pulled up to 3.3V/2.5V/1.8V matching the RGMII I/O voltage.
15	TXD3	input	RGMII transmit data bit 3 (MAC→PHY on TXD[3:0]). Internal pull-down.
16	TXD2	input	RGMII transmit data bit 2 (MAC→PHY on TXD[3:0]). Internal pull-down.
17	TXD1	input	RGMII transmit data bit 1 (MAC→PHY on TXD[3:0]). Internal pull-down.
18	TXD0	input	RGMII transmit data bit 0 (MAC→PHY on TXD[3:0]). Internal pull-down.
19	TX_CTL	input	RGMII transmit control signal from the MAC. Internal pull-down.
20	TX_CLK	input	RGMII transmit reference clock from MAC. 125 MHz / 25 MHz / 2.5 MHz depending on link speed. Internal pull-down.
21	DVDDL	power_in	Digital core power supply, 1.1V/1.2V. Fed from internal LDO2 output (pin 30) on YT8531DH.
22	RXD3/PHYAD0	output	RGMII receive data bit 3 (PHY→MAC on RXD[3:0]). At power-up latched as PHYAD[0] of the SMI PHY address. Internal pull-down.
23	RXD2/PLLOFF	output	RGMII receive data bit 2. Latched at power-up to configure PLL-off behavior in sleep mode. Internal pull-down.
24	RXD1/TXDLY	output	RGMII receive data bit 1. Latched at power-up: pull-up adds delay to TXC for TXD latching (RGMII TX clock timing). Internal pull-down.
25	RXD0/RXDLY	output	RGMII receive data bit 0. Latched at power-up: controls RGMII receive clock timing (adds 2 ns delay when RX_CLK=125MHz, 8 ns when RX_CLK=25/2.5MHz). Internal pull-up.
26	RX_CTL/PHYAD2	output	RGMII receive control signal to the MAC. Latched at power-up as PHYAD[2]. Internal pull-down.
27	RX_CLK/PHYAD1	output	RGMII continuous receive reference clock (125/25/2.5 MHz derived from received data). Latched at power-up as PHYAD[1]. Internal pull-down.
28	DVDD_RGMII	power_in	Digital RGMII I/O and MDC/MDIO pad power. Voltage set by CFG_EXT and CFG_LDO[1:0]: 3.3V/2.5V/1.8V from external supply, or from the internal LDO (2.5V/1.8V only). A bulk plus decoupling cap is required regardless of source.
29	DVDD33	power_in	3.3V digital non-RGMII I/O power supply.
30	LDO_O	power_out	Internal LDO output, 1.1V. On YT8531DH/YT8531DC this pin sources the 1.1V/1.2V core rail; connect to AVDDL (pins 3, 8, 38) and DVDDL (pin 21) with appropriate decoupling.
31	INT_N/PME_N	output	Open-drain interrupt / power-management event output. Default is INT_N (active-low level-triggered). Selectable to PME_N (Wake-on-LAN magic-packet event) via EXT 0xA00A bit[6]. Must be pulled up to 3.3V/2.5V/1.8V when used, or left floating.
32	LED0/CFG_EXT	output	LED0 output (default: link-up at 10 Mbps solid, activity blink). Latched at power-up as CFG_EXT: pull-up = use external I/O pad power; pull-down = use internal LDO. Internal pull-up.
33	LED1/CFG_LDO0	output	LED1 output (default: link-up at 100 Mbps solid, activity blink). Latched at power-up as CFG_LDO[0], setting internal LDO output voltage or external I/O voltage selection together with CFG_LDO1. Internal pull-up.
34	LED2/CFG_LDO1	output	LED2 output (default: link-up at 1000 Mbps solid, activity blink). Latched at power-up as CFG_LDO[1]. Together with CFG_LDO0: with CFG_EXT low selects internal LDO = 2.5V/1.8V; with CFG_EXT high selects external I/O = 3.3V/2.5V/1.8V. Internal pull-down.
35	CLKOUT	output	25 MHz reference clock output derived from the internal PLL. Also used as the UTP recovery receive clock for Sync-E. Leave floating if unused by the MAC.
36	XTAL_I	input	25 MHz crystal input. If driving from an external oscillator/clock on this pin, leave XTAL_O floating. If driving XTAL_O from an external source instead, tie XTAL_I to GND.
37	XTAL_O	output	25 MHz crystal output. When driving from an external oscillator/clock on this pin, XTAL_I must be shorted to GND.
38	AVDDL	power_in	Analog core power supply, 1.1V/1.2V. Third AVDDL pin; tie to same rail as pins 3 and 8.
39	RBIAS	passive	Bias resistor pin. An external 2.49 kΩ ±1% resistor must be connected between RBIAS and GND to set the internal bias current.
40	AVDD33	power_in	Analog 3.3V power supply (second AVDD33 pin; tie to same rail as pin 11).
41	GND	power_in	Exposed thermal pad on the package underside. Must be soldered to the PCB ground plane for both electrical ground and heat sinking.

Key specifications

Parameter	Value
Manufacturer	Motorcomm
Package	QFN-40(5x5)
Category	Interface
Pins	41

Ordering variants

Same part, different packaging or reel option.

YT8531DH-CA
YT8531DC-CA
YT8531H-CA
YT8531C-CA
YT8531P-CA

CAD (KiCad official)

Symbol: YT8531DH-CA
Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
3D model: QFN-40(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Motorcomm datasheet (66 pp, sha256 57f742224754da8c, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF