component
MC74ACT573DTR2G
Public Made by Adomby adom
onsemi Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74ACT573DTR2G
onsemi · Latches · TSSOP-20
MC74ACT573DTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | 3-state output enable input: when LOW the output buffers are enabled, and when HIGH they are in high-impedance mode without interfering with new data entering the latches. |
| 2 | D0 | input | Data input to latch 0; when LE is HIGH data on D0 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 3 | D1 | input | Data input to latch 1; when LE is HIGH data on D1 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 4 | D2 | input | Data input to latch 2; when LE is HIGH data on D2 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 5 | D3 | input | Data input to latch 3; when LE is HIGH data on D3 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 6 | D4 | input | Data input to latch 4; when LE is HIGH data on D4 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 7 | D5 | input | Data input to latch 5; when LE is HIGH data on D5 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 8 | D6 | input | Data input to latch 6; when LE is HIGH data on D6 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 9 | D7 | input | Data input to latch 7; when LE is HIGH data on D7 enters the transparent latch, and the ACT version has TTL-compatible inputs. |
| 10 | GND | power_in | Ground reference; all DC input, output and supply voltages are referenced to GND. |
| 11 | LE | input | Latch enable input: when HIGH the latches are transparent to Dn, and when LOW the latches store the data present at the D inputs. |
| 12 | O7 | tri_state | 3-state latch output 7 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 13 | O6 | tri_state | 3-state latch output 6 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 14 | O5 | tri_state | 3-state latch output 5 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 15 | O4 | tri_state | 3-state latch output 4 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 16 | O3 | tri_state | 3-state latch output 3 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 17 | O2 | tri_state | 3-state latch output 2 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 18 | O1 | tri_state | 3-state latch output 1 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 19 | O0 | tri_state | 3-state latch output 0 that can source and sink 24 mA (IOH −24 mA, IOL 24 mA). |
| 20 | VCC | power_in | Supply voltage: 2.0 to 6.0 V for AC and 4.5 to 5.5 V for ACT, per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (ACT) | VCC | 4.5 | 5 | 5.5 | V | ACT devices | 3 |
| DC Input/Output Voltage | VIN, VOUT | 0 | V | Referenced to GND; upper limit printed as VCC | 3 | ||
| Input Rise and Fall Time (ACT, except Schmitt inputs) | tr, tf | 10 | ns/V | VCC @ 4.5 V | 3 | ||
| Input Rise and Fall Time (ACT, except Schmitt inputs) | tr, tf | 8 | ns/V | VCC @ 5.5 V | 3 | ||
| Operating Ambient Temperature Range | TA | -40 | 25 | 85 | °C | 3 | |
| Output Current - High | IOH | -24 | mA | 3 | |||
| Output Current - Low | IOL | 24 | mA | 3 | |||
| DC Supply Voltage | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC Input Voltage | VIN | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 | ||
| DC Output Voltage | VOUT | -0.5 | V | Referenced to GND (Note 1); upper limit printed as VCC + 0.5 V | 3 | ||
| DC Input Diode Current | IIK | -20 | 20 | mA | 3 | ||
| DC Output Diode Current | IOK | -50 | 50 | mA | 3 | ||
| DC Output Sink/Source Current | IOUT | -50 | 50 | mA | 3 | ||
| DC Supply Current, per Output Pin | ICC | -50 | 50 | mA | Per output pin | 3 | |
| DC Ground Current, per Output Pin | IGND | -100 | 100 | mA | Per output pin | 3 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 3 | ||
| Junction Temperature Under Bias | TJ | 140 | °C | 3 | |||
| ESD Withstand Voltage (Human Body Model) | VESD | 2000 | V | Human Body Model; printed as > 2000 V | 3 | ||
| ESD Withstand Voltage (Machine Model) | VESD | 200 | V | Machine Model; printed as > 200 V | 3 | ||
| ESD Withstand Voltage (Charged Device Model) | VESD | 1000 | V | Charged Device Model; printed as > 1000 V | 3 | ||
| Latchup Performance | ILatchup | -100 | 100 | mA | Above VCC and below GND at 85 °C | 3 | |
| Thermal Resistance, Junction-to-Ambient (TSSOP) | θJA | 110.7 | °C/W | TSSOP package; per JESD 51-7 (Note 2) | 3 | ||
| Minimum High Level Input Voltage | VIH | 2 | V | VCC 4.5 V; TA = -40 °C to +85 °C; VOUT = 0.1 V or VCC - 0.1 V | 6 | ||
| Maximum Low Level Input Voltage | VIL | 0.8 | V | VCC 4.5 V; TA = -40 °C to +85 °C; VOUT = 0.1 V or VCC - 0.1 V | 6 | ||
| Minimum High Level Output Voltage | VOH | 4.4 | V | VCC 4.5 V; IOUT = -50 µA; TA = -40 °C to +85 °C | 6 | ||
| Minimum High Level Output Voltage | VOH | 5.4 | V | VCC 5.5 V; IOUT = -50 µA; TA = -40 °C to +85 °C | 6 | ||
| Minimum High Level Output Voltage | VOH | 3.76 | V | VCC 4.5 V; IOH = -24 mA; VIN = VIL or VIH; TA = -40 °C to +85 °C | 6 | ||
| Minimum High Level Output Voltage | VOH | 4.76 | V | VCC 5.5 V; IOH = -24 mA; VIN = VIL or VIH; TA = -40 °C to +85 °C | 6 | ||
| Maximum Low Level Output Voltage | VOL | 0.1 | V | VCC 4.5 V; IOUT = 50 µA; TA = -40 °C to +85 °C | 6 | ||
| Maximum Low Level Output Voltage | VOL | 0.44 | V | VCC 4.5 V; IOL = 24 mA; VIN = VIL or VIH; TA = -40 °C to +85 °C | 6 | ||
| Maximum Input Leakage Current | IIN | -1 | 1 | µA | VCC 5.5 V; VI = VCC, GND; TA = -40 °C to +85 °C | 6 | |
| Additional Max. ICC/Input | ICCT | 0.6 | 1.5 | mA | VCC 5.5 V; VI = VCC - 2.1 V | 6 | |
| Maximum 3-State Current | IOZ | -5 | 5 | µA | VCC 5.5 V; VI(OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND; TA = -40 °C to +85 °C | 6 | |
| Minimum Dynamic Output Current (LOW) | IOLD | 75 | mA | VCC 5.5 V; VOLD = 1.65 V Max | 6 | ||
| Minimum Dynamic Output Current (HIGH) | IOHD | -75 | mA | VCC 5.5 V; VOHD = 3.85 V Min | 6 | ||
| Maximum Quiescent Supply Current | ICC | 80 | µA | VCC 5.5 V; VIN = VCC or GND; TA = -40 °C to +85 °C | 6 | ||
| Propagation Delay Dn to On (tPLH) | tPLH | 2 | 12 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Propagation Delay Dn to On (tPHL) | tPHL | 2 | 12 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Propagation Delay LE to On (tPLH) | tPLH | 2.5 | 12 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Propagation Delay LE to On (tPHL) | tPHL | 2 | 10.5 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Output Enable Time (tPZH) | tPZH | 1.5 | 11 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Output Enable Time (tPZL) | tPZL | 1.5 | 10.5 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Output Disable Time (tPHZ) | tPHZ | 1.5 | 12.5 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Output Disable Time (tPLZ) | tPLZ | 1 | 9.5 | ns | VCC 5.0 V; CL = 50 pF; TA = -40 °C to +85 °C | 6 | |
| Setup Time, HIGH or LOW (Dn to LE) | ts | 3.5 | ns | VCC 5.0 V; TA = -40 °C to +85 °C | 7 | ||
| Hold Time, HIGH or LOW (Dn to LE) | th | 0 | ns | VCC 5.0 V; TA = -40 °C to +85 °C | 7 | ||
| LE Pulse Width, HIGH | tw | 4 | ns | VCC 5.0 V; TA = -40 °C to +85 °C | 7 |
CAD (KiCad official)
- Symbol:
MC74ACT573DTR2G - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
mc74act573dtr2g-etched.step/mc74act573dtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74act573dtr2g.step/mc74act573dtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (10 pp, sha256
553dcace17dc33e0, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).