AD5220BRZ10 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLK	input	Negative-edge-triggered serial clock input that steps the wiper one position per pulse while CS is active low, and the datasheet recommends a minimum negative-edge slew rate of 1 V/µs with external debounce.
2	U/D	input	UP/DOWN direction control input: logic high increments the wiper toward terminal A and logic low decrements it toward terminal B.
3	A1	passive	Terminal A of the variable resistor, with VA limited to 0 V to VDD relative to GND.
4	GND	power_in	Ground reference pin for the device.
5	W1	passive	Wiper terminal of the variable resistor, limited to 0 V to VDD relative to GND, with direct-contact current between W and B not to exceed 5 mA.
6	B1	passive	Terminal B of the variable resistor, limited to 0 V to VDD relative to GND.
7	CS	input	Chip select input, active low: clock pulses change the wiper only while CS is low, and the wiper position is fixed when CS is high.
8	VDD	power_in	Positive power supply, specified at 2.7 V to 5.5 V, with absolute maximum VDD to GND of -0.3 V to +7 V.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Resistor Differential Nonlinearity R-DNL (RAB = 10 kΩ)	R-DNL	-1	0.4	1	LSB	RWB, VA = NC, RAB = 10 kΩ	2
Resistor Nonlinearity R-INL (RAB = 10 kΩ)	R-INL	-1	0.5	1	LSB	RWB, VA = NC, RAB = 10 kΩ	2
Nominal Resistor Tolerance	ΔRAB	-30		30	%	ΔRAB/RAB, TA = +25°C	2
Resistance Temperature Coefficient	ΔRAB/ΔT		800		ppm/°C	VAB = VDD, Wiper = No Connect	2
Wiper Resistance	RW		40	100	Ω	IW = VDD/R, VDD = +3 V or +5 V	2
Integral Nonlinearity (RAB = 10 kΩ)	INL	-1	0.5	1	LSB	RAB = 10 kΩ	2
Differential Nonlinearity Error (RAB = 10 kΩ)	DNL	-1	0.4	1	LSB	RAB = 10 kΩ	2
Voltage Divider Temperature Coefficient	ΔVW/ΔT		20		ppm/°C	Code = 40H	2
Full-Scale Error	VWFSE	-2	-0.5	0	LSB	Code = 7FH	2
Zero-Scale Error	VWZSE	0	0.5	1	LSB	Code = 00H	2
Voltage Range (lower limit; upper limit is VDD)	VA, VB, VW	0			V	Upper limit VDD	2
Common-Mode Leakage	ICM			7.5	nA	VA = VB = VW	2
Input Logic High (VDD = +5 V)	VIH	2.4			V	VDD = +5 V	2
Input Logic High (VDD = +3 V)	VIH	2.1			V	VDD = +3 V	2
Input Logic Low (VDD = +5 V)	VIL			0.8	V	VDD = +5 V	2
Input Logic Low (VDD = +3 V)	VIL			0.6	V	VDD = +3 V	2
Input Current	IIL	-1		1	µA	VIN = 0 V or +5 V	2
Power Supply Range	VDD	2.7		5.5	V		2
Supply Current	IDD		15	40	µA	VIH = +5 V or VIL = 0 V, VDD = +5 V	2
Power Dissipation	PDISS		75	200	µW	VIH = +5 V or VIL = 0 V, VDD = +5 V	2
Power Supply Sensitivity	PSS		0.004	0.015	%/%		2
Clock Input Pulsewidth	tCH, tCL	25			ns	Clock Level High or Low	2
CS to CLK Setup Time	tCSS	20			ns		2
CS Rise to Clock Hold Time	tCSH	20			ns		2
U/D to Clock Fall Setup Time	tUDS	10			ns		2
Nominal Resistance (RAB)	RAB		10		kΩ	AD5220BRZ10 ordering guide, RAB (kΩ)	11
VDD to GND	VDD	-0.3		7	V		3
VA, VB, VW to GND	VA, VB, VW	0			V	Upper limit VDD	3
AX-BX, AX-WX, BX-WX Continuous Current		-20		20	mA		3
Digital Input Voltage to GND		0			V	Upper limit VDD + 0.3 V	3
Operating Temperature Range	TA	-40		85	°C		3
Maximum Junction Temperature	TJ MAX			150	°C		3
Storage Temperature		-65		150	°C		3
Lead Temperature (Soldering)				300	°C	10 sec	3
Thermal Resistance θJA	θJA		158		°C/W	SOIC (SO-8) package	3

CAD (KiCad official)

Symbol: AD5220BRZ10
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ad5220brz10-etched.step / ad5220brz10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5220brz10.step / ad5220brz10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (11 pp, sha256 bede8d49a9cd7eb4, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5220BRZ10

Verified AD5220BRZ10

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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