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STM32F373VCH7
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFBGA-100. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F373VCH7
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFBGA-100
STM32F373VCH7 from STMicroelectronics, in a UFBGA-100. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PE3 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TSC_G7_IO2 and TRACED0. |
| A2 | PE1 | bidirectional | 5 V tolerant (FT) I/O with alternate function USART1_RX. |
| A3 | PB8 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions SPI2_SCK/I2S2_CK, I2C1_SCL, USART3_TX, CAN_RX, CEC, TIM16_CH1, TIM4_CH3, TIM19_CH3, COMP1_OUT and TSC_SYNC. |
| A4 | BOOT0 | input | Dedicated BOOT0 input pin used for boot memory selection. |
| A5 | PD7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_SCK/I2S2_CK and USART2_CK. |
| A6 | PD5 | bidirectional | 5 V tolerant (FT) I/O with alternate function USART2_TX. |
| A7 | PB4 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_MISO/I2S1_MCK, SPI3_MISO/I2S3_MCK, USART2_RX, TIM16_CH1, TIM3_CH1, TIM17_BKIN, TIM15_CH1N, TSC_G5_IO2 and NJTRST. |
| A8 | PB3 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART2_TX, TIM2_CH2, TIM3_ETR, TIM4_ETR, TIM13_CH1, TSC_G5_IO1 and JTDO-TRACESWO. |
| A9 | PA15 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, I2C1_SCL, TIM2_CH1_ETR, TIM12_CH2, TSC_SYNC and JTDI. |
| A10 | PA14 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions I2C1_SDA, TIM12_CH1, TSC_G4_IO4 and SWCLK-JTCK. |
| A11 | PA13 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_MISO/I2S1_MCK, USART3_CTS, IR_OUT, TIM16_CH1N, TIM4_CH3, TIM5_CH4, TSC_G4_IO3 and SWDIO-JTMS. |
| A12 | PA12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_SCK/I2S1_CK, USART1_RTS, CAN_TX, USB_DP, TIM16_CH1, TIM4_CH2, TIM5_CH3 and COMP2_OUT. |
| B1 | PE4 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TSC_G7_IO3 and TRACED1. |
| B2 | PE2 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TSC_G7_IO1 and TRACECLK. |
| B3 | PB9 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions SPI2_NSS/I2S2_WS, I2C1_SDA, USART3_RX, CAN_TX, IR_OUT, TIM17_CH1, TIM4_CH4, TIM19_CH4 and COMP2_OUT. |
| B4 | PB7 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions I2C1_SDA, USART1_RX, TIM17_CH1N, TIM3_CH4, TIM4_CH2, TIM19_CH2, TIM15_CH2 and TSC_G5_IO4. |
| B5 | PB6 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions I2C1_SCL, USART1_TX, TIM16_CH1N, TIM3_CH3, TIM4_CH1, TIM19_CH1, TIM15_CH1 and TSC_G5_IO3. |
| B6 | PD6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_NSS/I2S2_WS and USART2_RX. |
| B7 | PD4 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MOSI/I2S2_SD and USART2_RTS. |
| B8 | PD3 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MISO/I2S2_MCK and USART2_CTS. |
| B9 | PD1 | bidirectional | 5 V tolerant (FT) I/O with alternate functions CAN_TX and TIM19_ETR. |
| B10 | PC12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI3_MOSI/I2S3_SD, USART3_CK and TIM19_CH3. |
| B11 | PC10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI3_SCK/I2S3_CK, USART3_TX and TIM19_CH1. |
| B12 | PA11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_NSS/I2S2_WS, SPI1_NSS/I2S1_WS, USART1_CTS, COMP1_OUT, CAN_RX, TIM4_CH1, USB_DM and TIM5_CH2. |
| C1 | PC13 | bidirectional | Standard 3.3 V I/O supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz with a 30 pF load and the pin must not be used as a current source; additional functions WKUP2, ALARM_OUT, CALIB_OUT, TIMESTAMP and RTC_TAMPER1. |
| C2 | PE5 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TSC_G7_IO4 and TRACED2. |
| C3 | PE0 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_TX and TIM4_ETR. |
| C4 | VDD_1 | power_in | Digital power supply. |
| C5 | PB5 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, I2C1_SMBA, USART2_CK, TIM16_BKIN, TIM3_CH2, TIM17_CH1 and TIM19_ETR. |
| C8 | PD2 | bidirectional | 5 V tolerant (FT) I/O with alternate function TIM3_ETR. |
| C9 | PD0 | bidirectional | 5 V tolerant (FT) I/O with alternate functions CAN_RX and TIM19_CH4. |
| C10 | PC11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI3_MISO/I2S3_MCK, USART3_RX and TIM19_CH2. |
| C11 | PF6 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions SPI1_MOSI/I2S1_SD, USART3_RTS, TIM4_CH4 and I2C2_SCL. |
| C12 | PA10 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions SPI2_MOSI/I2S2_SD, I2C2_SDA, USART1_RX, TIM2_CH4, TIM17_BKIN, TIM14_CH1 and TSC_G4_IO2. |
| D1 | PC14 | bidirectional | Standard 3.3 V I/O supplied through the power switch with the same 3 mA sink limit and output restrictions as PC13 (2 MHz, 30 pF, no current-source use), also used as OSC32_IN. |
| D2 | PE6 | bidirectional | 5 V tolerant (FT) I/O with alternate function TRACED3; additional functions WKUP3 and RTC_TAMPER3. |
| D3 | VSS_1 | power_in | Ground. |
| D10 | PA9 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate functions SPI2_MISO/I2S2_MCK, I2C2_SCL, USART1_TX, TIM2_CH3, TIM15_BKIN, TIM13_CH1 and TSC_G4_IO1. |
| D11 | PA8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_SCK/I2S2_CK, I2C2_SMBA, USART1_CK, TIM4_ETR, TIM5_CH1_ETR and MCO. |
| D12 | PC9 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_MOSI/I2S1_SD and TIM3_CH4. |
| E1 | PC15 | bidirectional | Standard 3.3 V I/O supplied through the power switch with the same 3 mA sink limit and output restrictions as PC13 (2 MHz, 30 pF, no current-source use), also used as OSC32_OUT. |
| E2 | VBAT | power_in | Backup power supply for the RTC and backup registers. |
| E3 | PF4 | bidirectional | 5 V tolerant (FT) I/O with no alternate or additional function listed in the pin definitions. |
| E10 | PC8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI1_MISO/I2S1_MCK and TIM3_CH3. |
| E11 | PC7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM3_CH2 and SPI1_SCK/I2S1_CK. |
| E12 | PC6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM3_CH1 and SPI1_NSS/I2S1_WS. |
| F1 | PF0 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate function I2C2_SDA and additional function OSC_IN. |
| F2 | PF9 | bidirectional | 5 V tolerant (FT) I/O with alternate function TIM14_CH1. |
| F11 | VSS_3 | power_in | Ground. |
| F12 | VSSSD | power_in | Ground for SDADC1, SDADC2 and SDADC3. |
| G1 | PF1 | bidirectional | 5 V tolerant (FTf) I/O, FM+ capable, with alternate function I2C2_SCL and additional function OSC_OUT. |
| G2 | PF10 | bidirectional | 5 V tolerant (FT) I/O with no alternate or additional function listed in the pin definitions. |
| G11 | VDD_3 | power_in | Digital power supply. |
| G12 | VDDSD12 | power_in | Power supply for SDADC1 and SDADC2. |
| H1 | PC0 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate function TIM5_CH1_ETR and additional function ADC_IN10. |
| H2 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor; device reset input / internal reset output (active low). |
| H3 | VDD_2 | power_in | Digital power supply. |
| H10 | PD15 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions TIM4_CH4 and TSC_G8_IO4 and additional function SDADC3_AIN0M. |
| H11 | PD14 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions TIM4_CH3 and TSC_G8_IO3 and additional function SDADC3_AIN0P. |
| H12 | PD13 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions TIM4_CH2 and TSC_G8_IO2 and additional functions SDADC3_AIN1P and SDADC3_AIN2M. |
| J1 | PF2 | bidirectional | 5 V tolerant (FT) I/O with alternate function I2C2_SMBA. |
| J2 | PC1 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate function TIM5_CH2 and additional function ADCIN11. |
| J3 | PC2 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI2_MISO/I2S2_MCK and TIM5_CH3 and additional function ADC_IN12. |
| J10 | PD12 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions USART3_RTS, TIM4_CH1 and TSC_G8_IO1 and additional function SDADC3_AIN2P. |
| J11 | PD11 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate function USART3_CTS and additional functions SDADC3_AIN3P and SDADC3_AIN4M. |
| J12 | PD10 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate function USART3_CK and additional function SDADC3_AIN4P. |
| K1 | VSSA/VREF- | power_in | Analog ground. |
| K2 | PC3 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI2_MOSI/I2S2_SD and TIM5_CH4 and additional function ADC_IN13. |
| K3 | PA2 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions COMP2_OUT, SPI3_MISO/I2S3_MCK, USART2_TX, TIM2_CH3, TIM15_CH1, TIM5_CH3, TIM19_CH3 and TSC_G1_IO3; additional functions ADC_IN2 and COMP2_INM. |
| K4 | PA5 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, TIM14_CH1, TIM12_CH2 and TSC_G2_IO2; additional functions ADC_IN5 and DAC1_OUT2. |
| K5 | PC4 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions TIM13_CH1, TSC_G3_IO1 and USART1_TX and additional function ADC_IN14. |
| K8 | PD9 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions USART3_RX and TSC_G6_IO4 and additional functions SDADC3_AIN5P and SDADC3_AIN6M. |
| K9 | PD8 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions SPI2_SCK/I2S2_CK, USART3_TX and TSC_G6_IO3 and additional function SDADC3_AIN6P. |
| K10 | PB15 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions SPI2_MOSI/I2S2_SD, TIM15_CH1N, TIM15_CH2, TIM12_CH2, TSC_G6_IO2 and RTC_REFIN; additional functions SDADC3_AIN7P and SDADC3_AIN8M. |
| K11 | PB14 | bidirectional | Standard 3.3 V I/O powered by VDDSD3, with alternate functions SPI2_MISO/I2S2_MCK, USART3_RTS, TIM15_CH1, TIM12_CH1 and TSC_G6_IO1 and additional function SDADC3_AIN8P. |
| K12 | VREFSD+ | power_in | External reference voltage for SDADC1, SDADC2 and SDADC3 (positive input). |
| L1 | VREF+ | power_in | Reference voltage for ADC, COMP and DAC. |
| L2 | PA0 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions USART2_CTS, TIM2_CH1_ETR, TIM5_CH1_ETR, TIM19_CH1, TSC_G1_IO1 and COMP1_OUT; additional functions RTC_TAMPER2, WKUP1, ADC_IN0 and COMP1_INM. |
| L3 | PA3 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI3_MOSI/I2S3_SD, USART2_RX, TIM2_CH4, TIM15_CH2, TIM5_CH4, TIM19_CH4 and TSC_G1_IO4; additional functions ADC_IN3 and COMP2_INP. |
| L4 | PA6 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI1_MISO/I2S1_MCK, COMP1_OUT, TIM3_CH1, TIM13_CH1, TIM16_CH1 and TSC_G2_IO3; additional functions ADC_IN6 and DAC2_OUT1. |
| L5 | PC5 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions TSC_G3_IO2 and USART1_RX and additional function ADC_IN15. |
| L6 | PB2 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC1_AIN4P and SDADC2_AIN6P. |
| L7 | PE8 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC1_AIN8P and SDADC2_AIN8P. |
| L8 | PE10 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional function SDADC1_AIN2P. |
| L9 | PE12 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC1_AIN0P, SDADC2_AIN3P and SDADC2_AIN4M. |
| L10 | PB10 | bidirectional | Standard 3.3 V I/O powered by VDDSD12, with alternate functions SPI2_SCK/I2S2_CK, USART3_TX, CEC, TSC_SYNC and TIM2_CH3; additional function SDADC2_AIN0M. |
| L11 | VREFSD- | power_in | External reference voltage for SDADC1, SDADC2 and SDADC3 (negative input), also the negative SDADC analog input in single-ended mode. |
| L12 | VDDSD3 | power_in | Power supply for SDADC3. |
| M1 | VDDA | power_in | Analog power supply. |
| M2 | PA1 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI3_SCK/I2S3_CK, USART2_RTS, TIM2_CH2, TIM15_CH1N, TIM5_CH2, TIM19_CH2, TSC_G1_IO2 and RTC_REFIN; additional functions ADC_IN1 and COMP1_INP. |
| M3 | PA4 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, TIM3_CH2, TIM12_CH1 and TSC_G2_IO1; additional functions ADC_IN4 and DAC1_OUT1. |
| M4 | PA7 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions TSC_G2_IO4, TIM14_CH1, SPI1_MOSI/I2S1_SD, TIM17_CH1, TIM3_CH2 and COMP2_OUT; additional function ADC_IN7. |
| M5 | PB0 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH3, TSC_G3_IO3 and TIM3_CH2; additional functions ADC_IN8 and SDADC1_AIN6P. |
| M6 | PB1 | bidirectional | 3.3 V tolerant I/O directly connected to ADC with alternate functions TIM3_CH4 and TSC_G3_IO4; additional functions ADC_IN9, SDADC1_AIN5P and SDADC1_AIN6M. |
| M7 | PE7 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC1_AIN3P, SDADC1_AIN4M, SDADC2_AIN5P and SDADC2_AIN6M. |
| M8 | PE9 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC1_AIN7P, SDADC1_AIN8M, SDADC2_AIN7P and SDADC2_AIN8M. |
| M9 | PE11 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC1_AIN1P, SDADC1_AIN2M and SDADC2_AIN4P. |
| M10 | PE13 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC1_AIN0M and SDADC2_AIN2P. |
| M11 | PE14 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with no alternate function; additional functions SDADC2_AIN1P and SDADC2_AIN2M. |
| M12 | PE15 | bidirectional | Standard 3.3 V I/O powered by VDDSD12 with alternate function USART3_RX and additional function SDADC2_AIN0P. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFBGA-100 |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
STM32F373VCH7 - Footprint:
Package_BGA:UFBGA-100_7x7mm_Layout12x12_P0.5mm - 3D model: UFBGA-100 (KiCad packages3D, STEP)
- 3D model files:
stm32f373vch7-etched.step/stm32f373vch7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f373vch7.step/stm32f373vch7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (137 pp, sha256
fd00ebf096b21764, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).