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AVR64EA48-I/PT

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrolleravr64ea48-ifactory-2.0.0extractor-text

Verified AVR64EA48-I/PT

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR64EA48-I/PT · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 565-page datasheet
  • ✓distributor: lcsc C7503036, digikey 150-AVR64EA48-I/PT-ND, mouser 556-AVR64EA48-I/PT
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-a_inmtcr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.553)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr64ea48-i-pt.kicad_sym✓ avr64ea48-i-pt.kicad_mod✓ avr64ea48-i-pt.step
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Contents

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AVR64EA48-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)

AVR64EA48-I from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA5 bidirectional General-purpose I/O pin PA5 on PORTA, multiplexed with ADC0 AIN25, USART0 RxD, SPI0 MISO and TCA0 WO5 (alternate positions via PORTMUX).
2 PA6 bidirectional General-purpose I/O pin PA6 on PORTA, multiplexed with ADC0 AIN26, USART0 XCK, SPI0 SCK and CCL LUT0 OUT (alternate positions via PORTMUX).
3 PA7 bidirectional General-purpose I/O pin PA7 on PORTA, multiplexed with CLKOUT, ADC0 AIN27, SPI0 SS and EVSYS EVOUTA (alternate positions via PORTMUX).
4 PB0 bidirectional General-purpose I/O pin PB0 on PORTB, multiplexed with TCA0 WO0 (alternate position via PORTMUX).
5 PB1 bidirectional General-purpose I/O pin PB1 on PORTB, multiplexed with TCA0 WO1 (alternate position via PORTMUX).
6 PB2 bidirectional General-purpose I/O pin PB2 on PORTB, multiplexed with TCA0 WO2 and EVSYS EVOUTB (alternate positions via PORTMUX).
7 PB3 bidirectional General-purpose I/O pin PB3 on PORTB, multiplexed with TCA0 WO3 (alternate position via PORTMUX).
8 PB4 bidirectional General-purpose I/O pin PB4 on PORTB, multiplexed with TCA0 WO4 (alternate position via PORTMUX).
9 PB5 bidirectional General-purpose I/O pin PB5 on PORTB, multiplexed with TCA0 WO5 (alternate position via PORTMUX).
10 PC0 bidirectional General-purpose I/O pin PC0 on PORTC, multiplexed with ADC0 AIN28, USART1 TxD, SPI0 MOSI/SCK and CCL LUT1 IN0 (alternate positions via PORTMUX).
11 PC1 bidirectional General-purpose I/O pin PC1 on PORTC, multiplexed with ADC0 AIN29, USART1 RxD, SPI0 MISO/SS and CCL LUT1 IN1 (alternate positions via PORTMUX).
12 PC2 bidirectional General-purpose I/O pin PC2 on PORTC, multiplexed with ADC0 AIN30, AC negative input AINN3, USART1 XCK, SPI0 SCK, TWI0 SDA and CCL LUT1 IN2 (alternate positions via PORTMUX).
13 PC3 bidirectional General-purpose I/O pin PC3 on PORTC, multiplexed with ADC0 AIN31, AC positive input AINP4, USART1 XDIR, SPI0 SS, TWI0 SCL and CCL LUT1 OUT (alternate positions via PORTMUX).
14 VDD power_in Supply voltage for I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD pins.
15 GND power_in Ground pin, which must be connected to the same ground plane as all other GND pins.
16 PC4 bidirectional General-purpose I/O pin PC4 on PORTC, multiplexed with USART1 TxD, TCA0 WO4 and TCA0 WO0 (alternate positions via PORTMUX).
17 PC5 bidirectional General-purpose I/O pin PC5 on PORTC, multiplexed with USART1 RxD, TCA0 WO5 and TCA0 WO1 (alternate positions via PORTMUX).
18 PC6 bidirectional General-purpose I/O pin PC6 on PORTC, multiplexed with CCL LUT1 OUT, USART1 XCK, TWI0 SDA, TCA0 WO2 and analog comparator output (alternate positions via PORTMUX).
19 PC7 bidirectional General-purpose I/O pin PC7 on PORTC, multiplexed with USART1 XDIR, TWI0 SCL and EVSYS EVOUTC (alternate positions via PORTMUX).
20 PD0 bidirectional General-purpose I/O pin PD0 on PORTD, multiplexed with ADC0 AIN0, AC negative input AINN1, TCA0 WO0 and CCL LUT2 IN0.
21 PD1 bidirectional General-purpose I/O pin PD1 on PORTD, multiplexed with ADC0 AIN1, TCA0 WO1 and CCL LUT2 IN1.
22 PD2 bidirectional General-purpose I/O pin PD2 on PORTD, multiplexed with ADC0 AIN2, AC positive input AINP0, TCA0 WO2, CCL LUT2 IN2 and EVSYS EVOUTD.
23 PD3 bidirectional General-purpose I/O pin PD3 on PORTD, multiplexed with ADC0 AIN3, AC negative input AINN0, TCA0 WO3 and CCL LUT2 OUT.
24 PD4 bidirectional General-purpose I/O pin PD4 on PORTD, multiplexed with ADC0 AIN4, AC positive input AINP2, USART0 TxD, SPI0 MOSI and TCA0 WO4 (alternate positions via PORTMUX).
25 PD5 bidirectional General-purpose I/O pin PD5 on PORTD, multiplexed with ADC0 AIN5, AC negative input AINN0, USART0 RxD, SPI0 MISO and TCA0 WO5 (alternate positions via PORTMUX).
26 PD6 bidirectional General-purpose I/O pin PD6 on PORTD, multiplexed with ADC0 AIN6, AC positive input AINP3, analog comparator output, USART0 XCK, USART0 TxD, SPI0 SCK, TCA0 WO2 and CCL LUT2 OUT (alternate positions via PORTMUX).
27 PD7 bidirectional General-purpose I/O pin PD7 on PORTD, multiplexed with the VREFA external reference input, ADC0 AIN7, AC negative input AINN2, USART0 XDIR, USART0 RxD, SPI0 SS and EVSYS EVOUTD (alternate positions via PORTMUX).
28 VDD power_in Supply voltage for I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD pins.
29 GND power_in Ground pin, which must be connected to the same ground plane as all other GND pins.
30 PE0 bidirectional General-purpose I/O pin PE0 on PORTE, multiplexed with ADC0 AIN8, AC positive input AINP1, SPI0 MOSI and TCA0 WO0 (alternate positions via PORTMUX).
31 PE1 bidirectional General-purpose I/O pin PE1 on PORTE, multiplexed with ADC0 AIN9, SPI0 MISO and TCA0 WO1 (alternate positions via PORTMUX).
32 PE2 bidirectional General-purpose I/O pin PE2 on PORTE, multiplexed with ADC0 AIN10, AC positive input AINP2, SPI0 SCK, TCA0 WO2 and EVSYS EVOUTE (alternate positions via PORTMUX).
33 PE3 bidirectional General-purpose I/O pin PE3 on PORTE, multiplexed with ADC0 AIN11, SPI0 SS and TCA0 WO3 (alternate positions via PORTMUX).
34 PF0 bidirectional General-purpose I/O pin PF0 on PORTF, multiplexed with XTAL32K1 (32.768 kHz crystal), ADC0 AIN16, USART2 TxD, TCA0 WO0 and CCL LUT3 IN0 (alternate positions via PORTMUX).
35 PF1 bidirectional General-purpose I/O pin PF1 on PORTF, multiplexed with XTAL32K2 (32.768 kHz crystal), ADC0 AIN17, USART2 RxD, TCA0 WO1 and CCL LUT3 IN1 (alternate positions via PORTMUX).
36 PF2 bidirectional General-purpose I/O pin PF2 on PORTF, multiplexed with ADC0 AIN18, USART2 XCK, TCA0 WO2, CCL LUT3 IN2 and EVSYS EVOUTF.
37 PF3 bidirectional General-purpose I/O pin PF3 on PORTF, multiplexed with ADC0 AIN19, USART2 XDIR, TCA0 WO3 and CCL LUT3 OUT.
38 PF4 bidirectional General-purpose I/O pin PF4 on PORTF, multiplexed with ADC0 AIN20, USART2 TxD, TCA0 WO4 and TCA0 WO (alternate positions via PORTMUX).
39 PF5 bidirectional General-purpose I/O pin PF5 on PORTF, multiplexed with ADC0 AIN21, USART2 RxD and TCA0 WO5 (alternate positions via PORTMUX).
40 PF6 input PF6 is the RESET pin (also the HV programming input) and is input only, per the note to Table 3-1; the RESET function is selected by the RSTPINCFG fuse.
41 PF7 bidirectional General-purpose I/O pin PF7 on PORTF, which is the UPDI programming/debug pin and can alternatively be used for SPI0 SS and EVSYS EVOUTF (UPDIPINCFG fuse selects UPDI or GPIO at start-up).
42 VDD power_in Supply voltage for I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD pins.
43 GND power_in Ground pin, which must be connected to the same ground plane as all other GND pins.
44 PA0 bidirectional General-purpose I/O pin PA0 on PORTA, multiplexed with XTALHF1 (high-frequency crystal), EXTCLK, USART0 TxD, SPI0 MOSI, TWI0 SDA, TCA0 WO0 and CCL LUT0 IN0 (alternate positions via PORTMUX).
45 PA1 bidirectional General-purpose I/O pin PA1 on PORTA, multiplexed with XTALHF2 (high-frequency crystal), USART0 RxD, SPI0 MISO, TWI0 SCL, TCA0 WO1 and CCL LUT0 IN1 (alternate positions via PORTMUX).
46 PA2 bidirectional General-purpose I/O pin PA2 on PORTA, multiplexed with ADC0 AIN22, USART0 XCK, USART0 TxD, TWI0 SDA, TCA0 WO2, CCL LUT0 IN2 and EVSYS EVOUTA (alternate positions via PORTMUX).
47 PA3 bidirectional General-purpose I/O pin PA3 on PORTA, multiplexed with ADC0 AIN23, USART0 XDIR, USART0 RxD, TWI0 SCL, TCA0 WO3 and CCL LUT0 OUT (alternate positions via PORTMUX).
48 PA4 bidirectional General-purpose I/O pin PA4 on PORTA, multiplexed with ADC0 AIN24, USART0 TxD, SPI0 MOSI and TCA0 WO4 (alternate positions via PORTMUX).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-48(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (device operating range, AVR64EA48-I/PT TQFP-48) 1.8 5.5 V 526
Operating temperature range (-I industrial grade) -40 85 °C 526

CAD (KiCad official)

  • Symbol: AVR64EA48-I
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: avr64ea48-i-pt-etched.step / avr64ea48-i-pt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr64ea48-i-pt.step / avr64ea48-i-pt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (565 pp, sha256 1a38a4e7aeeb9404, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF