CY8C5666AXI-LP001 from Cypress Semicon, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P2[5]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces, also Cortex-M3 TRACEPORT output TRACEDATA[1]; analog voltage must not exceed its VDDIO2 supply.
2	P2[6]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces, also Cortex-M3 TRACEPORT output TRACEDATA[2]; analog voltage must not exceed its VDDIO2 supply.
3	P2[7]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces, also Cortex-M3 TRACEPORT output TRACEDATA[3]; analog voltage must not exceed its VDDIO2 supply.
4	P12[4]	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered, used as I2C0 SCL with wake from sleep on address match.
5	P12[5]	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered, used as I2C0 SDA with wake from sleep on address match.
6	P6[4]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
7	P6[5]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
8	P6[6]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
9	P6[7]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
10	VSSB	power_in	Ground connection for the boost pump.
11	IND	passive	Inductor connection to the boost pump.
12	VBOOST	input	Power sense connection to the boost pump.
13	VBAT	power_in	Battery supply to the boost pump.
14	VSSD	power_in	Ground for all digital logic and I/O pins.
15	XRES	input	External reset pin, active low with internal pull-up.
16	P5[0]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
17	P5[1]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
18	P5[2]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
19	P5[3]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
20	P1[0], SWDIO, TMS	bidirectional	General purpose I/O, also JTAG Test Mode Select (TMS) and Serial Wire Debug Input/Output (SWDIO); analog voltage must not exceed its VDDIO supply.
21	P1[1], SWDCK, TCK	bidirectional	General purpose I/O, also JTAG Test Clock (TCK) and Serial Wire Debug Clock (SWDCK); analog voltage must not exceed its VDDIO supply.
22	P1[2]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
23	P1[3], SWV, TDO	bidirectional	General purpose I/O, also JTAG Test Data Out (TDO) and Single Wire Viewer output (SWV); analog voltage must not exceed its VDDIO supply.
24	P1[4], TDI	bidirectional	General purpose I/O, also JTAG Test Data In (TDI) programming and debug port; analog voltage must not exceed its VDDIO supply.
25	P1[5], NTRST	bidirectional	General purpose I/O, also optional JTAG Test Reset (NTRST) to reset the JTAG connection; analog voltage must not exceed its VDDIO supply.
26	VDDIO1	power_in	Supply for I/O pins of VDDIO1 (P1[7:0], P5[7:0], P12[7:6]); must be 1.71 V to 5.5 V and less than or equal to VDDA.
27	P1[6]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
28	P1[7]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
29	P12[6], SIO	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered; can act as an analog comparator.
30	P12[7], SIO	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered; can act as an analog comparator.
31	P5[4]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
32	P5[5]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
33	P5[6]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
34	P5[7]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO supply.
35	USB D+, P15[6]	unconnected	USB D+ pin is Do Not Use on devices without USB; this LP001 part has 0 USBIO pins, so the pin must be left floating.
36	USB D-, P15[7]	unconnected	USB D- pin is Do Not Use on devices without USB; this LP001 part has 0 USBIO pins, so the pin must be left floating.
37	VDDD	power_in	Supply for all digital peripherals and digital core regulator; must be less than or equal to VDDA and the two VDDD pins must be connected together.
38	VSSD	power_in	Ground for all digital logic and I/O pins.
39	VCCD	power_out	Output of the digital core regulator (or input in externally regulated mode, limited to 1.71 V to 1.89 V); the two VCCD pins must be shorted together with a 1 µF capacitor to VSSD.
40	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
41	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
42	P15[0]	passive	4 to 25 MHz crystal oscillator XO pin (also general purpose I/O).
43	P15[1]	passive	4 to 25 MHz crystal oscillator XI pin (also general purpose I/O).
44	P3[0], IDAC1	bidirectional	General purpose I/O and low-resistance output pin for high current IDAC1; analog voltage must not exceed its VDDIO3 supply.
45	P3[1], IDAC3	bidirectional	General purpose I/O and low-resistance output pin for high current IDAC3; analog voltage must not exceed its VDDIO3 supply.
46	P3[2], OA3-, REF1	bidirectional	General purpose I/O, also inverting input to uncommitted opamp 3 and external reference input Extref1; analog voltage must not exceed its VDDIO3 supply.
47	P3[3], OA3+	bidirectional	General purpose I/O, also noninverting input to uncommitted opamp 3; analog voltage must not exceed its VDDIO3 supply.
48	P3[4], OA1-	bidirectional	General purpose I/O, also inverting input to uncommitted opamp 1; analog voltage must not exceed its VDDIO3 supply.
49	P3[5], OA1+	bidirectional	General purpose I/O, also noninverting input to uncommitted opamp 1; analog voltage must not exceed its VDDIO3 supply.
50	VDDIO3	power_in	Supply for I/O pins of VDDIO3 (P3[7:0], P12[1:0], P15[3:0]); must be 1.71 V to 5.5 V and less than or equal to VDDA.
51	OA1OUT, P3[6]	bidirectional	General purpose I/O, also high current output of uncommitted opamp 1; not recommended for use with CapSense.
52	OA3OUT, P3[7]	bidirectional	General purpose I/O, also high current output of uncommitted opamp 3; not recommended for use with CapSense.
53	P12[0]	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered, used as I2C1 SCL.
54	P12[1]	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered, used as I2C1 SDA.
55	P15[2]	passive	32.768 kHz crystal oscillator XO pin (also general purpose I/O).
56	P15[3]	passive	32.768 kHz crystal oscillator XI pin (also general purpose I/O).
57	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
58	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
59	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
60	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
61	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
62	NC	unconnected	Labeled NC in the 100-pin TQFP pinout; the datasheet gives no function for this pin.
63	VCCA	power_out	Output of the analog core regulator (or input in externally regulated mode, limited to 1.71 V to 1.89 V); requires a 1 µF capacitor to VSSA and is not designed to drive external circuits.
64	VSSA	power_in	Ground for all analog peripherals.
65	VDDA	power_in	Supply for all analog peripherals and analog core regulator; must be the highest voltage present on the device.
66	VSSD	power_in	Ground for all digital logic and I/O pins.
67	P12[2]	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered; can act as an analog comparator.
68	P12[3]	bidirectional	Special I/O with programmable high threshold, high sink current and high-impedance input when unpowered; can act as an analog comparator.
69	P4[0]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
70	P4[1]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
71	OA2OUT, P0[0]	bidirectional	General purpose I/O, also high current output of uncommitted opamp 2; not recommended for use with CapSense.
72	OA0OUT, P0[1]	bidirectional	General purpose I/O, also high current output of uncommitted opamp 0; not recommended for use with CapSense.
73	OA0+, SAR1REF, P0[2]	bidirectional	General purpose I/O, also noninverting input to uncommitted opamp 0 and external reference for SAR1 ADC; analog voltage must not exceed its VDDIO0 supply.
74	OA0-, REF0, P0[3]	bidirectional	General purpose I/O, also inverting input to uncommitted opamp 0 and external reference input Extref0; analog voltage must not exceed its VDDIO0 supply.
75	VDDIO0	power_in	Supply for I/O pins of VDDIO0 (P0[7:0], P4[7:0], P12[3:2]); must be 1.71 V to 5.5 V and less than or equal to VDDA.
76	OA2+, SAR0REF, P0[4]	bidirectional	General purpose I/O, also noninverting input to uncommitted opamp 2 and external reference for SAR0 ADC; analog voltage must not exceed its VDDIO0 supply.
77	OA2-, P0[5]	bidirectional	General purpose I/O, also inverting input to uncommitted opamp 2; analog voltage must not exceed its VDDIO0 supply.
78	IDAC0, P0[6]	bidirectional	General purpose I/O and low-resistance output pin for high current IDAC0; analog voltage must not exceed its VDDIO0 supply.
79	IDAC2, P0[7]	bidirectional	General purpose I/O and low-resistance output pin for high current IDAC2; analog voltage must not exceed its VDDIO0 supply.
80	P4[2]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
81	P4[3]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
82	P4[4]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
83	P4[5]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
84	P4[6]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
85	P4[7]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO0 supply.
86	VCCD	power_out	Output of the digital core regulator (or input in externally regulated mode, limited to 1.71 V to 1.89 V); the two VCCD pins must be shorted together with a 1 µF capacitor to VSSD.
87	VSSD	power_in	Ground for all digital logic and I/O pins.
88	VDDD	power_in	Supply for all digital peripherals and digital core regulator; must be less than or equal to VDDA and the two VDDD pins must be connected together.
89	P6[0]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
90	P6[1]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
91	P6[2]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
92	P6[3]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
93	P15[4]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
94	P15[5]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
95	P2[0]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
96	P2[1]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
97	P2[2]	bidirectional	General purpose I/O for CPU, digital, analog, interrupt, LCD and CapSense interfaces; analog voltage must not exceed its VDDIO2 supply.
98	P2[3]	bidirectional	General purpose I/O, also Cortex-M3 TRACEPORT clock output TRACECLK; analog voltage must not exceed its VDDIO2 supply.
99	P2[4]	bidirectional	General purpose I/O, also Cortex-M3 TRACEPORT output TRACEDATA[0]; analog voltage must not exceed its VDDIO2 supply.
100	VDDIO2	power_in	Supply for I/O pins of VDDIO2 (P2[7:0], P6[7:0], P12[5:4], P15[5:4]); must be 1.71 V to 5.5 V and less than or equal to VDDA.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	LQFP-100(14x14)
Category	Electronic Tools/Instruments/Consumables
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog supply voltage relative to VSSA	VDDA	-0.5		6	V	relative to VSSA	67
Digital supply voltage relative to VSSD	VDDD	-0.5		6	V	relative to VSSD	67
I/O supply voltage relative to VSSD	VDDIO	-0.5		6	V	relative to VSSD	67
Direct analog core voltage input	VCCA	-0.5		1.95	V		67
Direct digital core voltage input	VCCD	-0.5		1.95	V		67
DC input voltage on SIO	VSIO			7	V	Output disabled	67
DC input voltage on SIO	VSIO			6	V	Output enabled	67
Voltage at boost converter input	VIND	0.5		5.5	V		67
Boost converter supply	VBAT			5.5	V		67
Current per VDDIO supply pin	IVDDIO			100	mA		67
GPIO current	IGPIO	-30		41	mA		67
SIO current	ISIO	-49		28	mA		67
Latch up current	LU	-140		140	mA		67
Electrostatic discharge voltage	ESDHBM	2000			V	Human Body Model	67
Electrostatic discharge voltage	ESDCDM	500			V	Charge Device Model	67
Analog supply voltage and input to analog core regulator	VDDA	1.8		5.5	V	Analog core regulator enabled	68
Analog supply voltage, analog regulator bypassed	VDDA	1.71	1.8	1.89	V	Analog core regulator disabled	68
Digital supply voltage relative to VSSD	VDDD	1.8			V	Digital core regulator enabled	68
Digital supply voltage, digital regulator bypassed	VDDD	1.71	1.8	1.89	V	Digital core regulator disabled	68
I/O supply voltage relative to VSSIO	VDDIO	1.71			V		68
Direct analog core voltage input (Analog regulator bypass)	VCCA	1.71	1.8	1.89	V	Analog core regulator disabled	68
Direct digital core voltage input (Digital regulator bypass)	VCCD	1.71	1.8	1.89	V	Digital core regulator disabled	68
Active mode current (IMO enabled, CPU executing complex program from flash)	IDD		2	3.8	mA	VDDX = 2.7 V to 5.5 V; FCPU = 3 MHz; T = 105 °C	68
Active mode current (IMO enabled, CPU executing complex program from flash)	IDD		3.2	5	mA	VDDX = 2.7 V to 5.5 V; FCPU = 6 MHz; T = 105 °C	68
Active mode current (IMO enabled, CPU executing complex program from flash)	IDD		15.7	17.25	mA	VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz; T = 105 °C	68
Active mode current (IMO enabled, CPU executing complex program from flash)	IDD		22.5	25.5	mA	VDDX = 2.7 V to 5.5 V; FCPU = 80 MHz, IMO = 3 MHz with PLL; T = 105 °C	68
Digital core regulator input voltage	VDDD	1.8		5.5	V		72
Digital core regulator output capacitor		0.9	1	1.1	µF	±10%, X5R ceramic or better	72
Analog core regulator input voltage	VDDA	1.8		5.5	V		72
Analog core regulator output capacitor		0.9	1	1.1	µF	±10%, X5R ceramic or better	72
Boost output voltage	VOUT	1.71	1.8	1.89	V	vsel = 1.8 V in register BOOST_CR0	73
Boost output voltage	VOUT	1.81	1.9	2	V	vsel = 1.9 V in register BOOST_CR0	73
Boost output voltage	VOUT	1.9	2	2.1	V	vsel = 2.0 V in register BOOST_CR0	73
Boost output voltage	VOUT	2.16	2.4	2.64	V	vsel = 2.4 V in register BOOST_CR0	73
Boost output voltage	VOUT	2.43	2.7	2.97	V	vsel = 2.7 V in register BOOST_CR0	73
Boost output voltage	VOUT	2.7	3	3.3	V	vsel = 3.0 V in register BOOST_CR0	73
Boost output voltage	VOUT	2.97	3.3	3.63	V	vsel = 3.3 V in register BOOST_CR0	73
Boost output voltage	VOUT	3.24	3.6	3.96	V	vsel = 3.6 V in register BOOST_CR0	73
Boost output voltage	VOUT	4.5	5	5.5	V	vsel = 5.0 V in register BOOST_CR0	73
Input voltage to boost	VBAT	0.5		0.8	V	IOUT = 0 mA-5 mA vsel = 1.8 V-2.0 V, TA = 0 °C-70 °C	73
Input voltage to boost	VBAT	1.6		3.6	V	IOUT = 0 mA-15 mA vsel = 1.8 V-5.0 V, TA = -10 °C-85 °C	73
Input voltage to boost	VBAT	0.8		1.6	V	IOUT = 0 mA-25 mA vsel = 1.8 V-2.7 V, TA = -10 °C-85 °C	73
Input voltage to boost	VBAT	1.8		2.5	V	IOUT = 0 mA-50 mA vsel = 1.8 V-3.3 V, TA = -40 °C-85 °C	73
Input voltage to boost	VBAT	1.3		2.5	V	vsel = 1.8 V-3.3 V, TA = -10 °C-85 °C	73
Input voltage to boost	VBAT	2.5		3.6	V	vsel = 2.5 V-5.0 V, TA = -10 °C-85 °C	73
Inductor peak current	ILPK			700	mA		73
Load regulation	RegLOAD			10	%		73
Line regulation	RegLINE			10	%		73
Boost inductor	LBOOST	3.7	4.7	5.7	µH	4.7 µH nominal	73
Boost inductor	LBOOST	8	10	12	µH	10 µH nominal	73
Boost inductor	LBOOST	17	22	27	µH	22 µH nominal	73
Total capacitance sum of VDDD, VDDA, VDDIO	CBOOST	17	26	31	µF		73
Battery filter capacitor	CBAT	17	22	27	µF		73
Schottky diode average forward current	IF	1			A		73
Schottky reverse voltage	VR	20			V		73
XRES pull up resistor	Rpullup	3.5	5.6	8.5	kΩ		83
Current through protection diode to VDDIO and VSSIO	Idiode			100	µA		83
Reset pulse width	TRESET	1			µs		83
Ambient temperature (electrical specifications valid range)	TA	-40		105	°C	Specifications valid for -40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted	67
Junction temperature (electrical specifications valid range)	TJ			120	°C	Specifications valid for TJ ≤ 120 °C, except where noted	67

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		gold	lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the ma	121

CAD (KiCad official)

Symbol: CY8C5666AXI-LP001
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: cy8c5666axi-lp001-etched.step / cy8c5666axi-lp001-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c5666axi-lp001.step / cy8c5666axi-lp001.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (132 pp, sha256 ccfd25ac696db40c, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY8C5666AXI-LP001

Changed since verified CY8C5666AXI-LP001

Verification log 1 record

3D Model

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