component
DAC60504BRTER
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownDAC60504BRTER
Texas Instruments · Digital To Analog Converters (DACs) · WQFN-16-EP(3x3)
DAC60504BRTER from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF | bidirectional | Reference output voltage pin when using the internal reference (default), or reference input pin when using an external reference. |
| 2 | OUT0 | output | Analog output voltage from DAC 0. |
| 3 | OUT1 | output | Analog output voltage from DAC 1. |
| 4 | OUT2 | output | Analog output voltage from DAC 2. |
| 5 | OUT3 | output | Analog output voltage from DAC 3. |
| 6 | GND | power_in | Ground reference point for all circuitry on the device. |
| 7 | VDD | power_in | Analog supply voltage, 2.7 V to 5.5 V. |
| 8 | GAIN | input | Sets initial buffer gain after power-up or reset: tied to GND gives gain of 1, tied to VIO gives gain of 2; changing it after power-up has no effect. |
| 9 | RSTSEL | input | Reset select: tied to GND all four DACs reset to zero scale, tied to VIO they reset to midscale. |
| 10 | REFDIV | input | Sets reference divider after power-up or reset: tied to GND the reference is not divided, tied to VIO it is divided by 2; changing it after power-up has no effect. |
| 11 | LDAC | input | A high-to-low transition updates the outputs of channels in synchronous mode simultaneously; the pin can be tied permanently to GND. |
| 12 | CS | input | Active-low serial data enable and frame synchronization signal; going low enables the serial interface input shift register. |
| 13 | SCLK | input | Serial interface clock. |
| 14 | SDI | input | Serial interface data input, clocked into the input shift register on each falling edge of SCLK. |
| 15 | SDO/ALARM | output | Serial data output (default, high impedance when CS is high) or open-drain ALARM output for CRC or reference alarm, which requires a 10 kΩ pull-up resistor to VIO. |
| 16 | VIO | power_in | IO supply voltage, 1.7 V to 5.5 V, setting the serial interface I/O operating voltage. |
| 17 | Thermal Pad | passive | Thermal pad on the bottom of the package; connect to an internal PCB ground plane using multiple vias for good thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16-EP(3x3) |
| Category | Data Converters |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | 6 | V | 6 | ||
| VIO to GND | VIO | -0.3 | 6 | V | 6 | ||
| DAC outputs to GND | -0.3 | V | max printed as VDD + 0.3 | 6 | |||
| REF to GND | -0.3 | V | max printed as VDD + 0.3 | 6 | |||
| Digital pins to GND | -0.3 | V | max printed as VIO + 0.3 | 6 | |||
| Input current to any pin except supply pins | -10 | 10 | mA | 6 | |||
| Operating free-air temperature | TA | -40 | 125 | °C | 6 | ||
| Junction temperature | TJ | -40 | 150 | °C | 6 | ||
| Storage temperature | Tstg | -60 | 150 | °C | 6 | ||
| ESD HBM | V(ESD) | -3000 | 3000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001 | 6 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | Charged-device model, JESD22-C101 | 6 | |
| Analog supply voltage | VDD | 2.7 | 5.5 | V | 6 | ||
| IO supply voltage | VIO | 1.7 | 5.5 | V | 6 | ||
| Digital input voltage | 0 | V | max printed as VIO | 6 | |||
| Reference input voltage, divider disabled | VREFIN | 1.2 | V | VDD = 3.3 V to 5.5 V; max printed as VDD/2 | 6 | ||
| Reference input voltage, divider enabled | VREFIN | 2.4 | V | VDD = 3.3 V to 5.5 V; max printed as VDD | 6 | ||
| Operating free-air temperature | TA | -40 | 125 | °C | 6 | ||
| Integral nonlinearity DAC60504 | INL | -1 | 0.5 | 1 | LSB | 7 | |
| Differential nonlinearity DAC60504 | DNL | -1 | 0.5 | 1 | LSB | specified 12-bit monotonic | 7 |
| Total unadjusted error | TUE | -0.1 | 0.05 | 0.1 | %FSR | 7 | |
| Offset error | -1.5 | 0.75 | 1.5 | mV | 7 | ||
| Zero-code error | 0.5 | 1.5 | mV | DAC code = zero scale | 7 | ||
| Full-scale error | -0.1 | 0.05 | 0.1 | %FSR | 7 | ||
| Gain error | -0.1 | 0.05 | 0.1 | %FSR | 7 | ||
| Reference output voltage | VREFOUT | 2.495 | 2.5 | 2.505 | V | TA = 25°C | 9 |
| Reference output drift | 2 | 5 | ppm/°C | 9 | |||
| High-level input voltage | VIH | 0.7 | × VIO | 9 | |||
| Low-level input voltage | VIL | 0.3 | × VIO | 9 | |||
| Input current | -2 | 2 | µA | 9 | |||
| Low-level output voltage | VOL | 0.4 | V | ILOAD = -0.2 mA | 9 | ||
| VDD supply current, internal reference enabled | IDD | 2.8 | 3.6 | mA | Active mode, internal reference enabled, gain = 1, DAC code = full scale, outputs unloaded, SPI static | 9 | |
| VDD supply current, internal reference disabled | IDD | 2.3 | 3 | mA | Active mode, internal reference disabled, gain = 1, DAC code = full scale, outputs unloaded, SPI static | 9 | |
| VIO supply current | IIO | 2 | 3 | µA | 9 | ||
| VDD supply current, power-down | IDD | 15 | µA | Power-down | 9 | ||
| Resolution DAC60504 | 12 | Bits | 7 | ||||
| Offset error drift | 1 | µV/°C | ±1 as printed | 7 | |||
| Zero-code error drift | 2 | µV/°C | ±2 as printed | 7 | |||
| Full-scale error drift | 2 | ppm of FSR/°C | ±2 as printed | 7 | |||
| Gain error drift | 1 | ppm of FSR/°C | ±1 as printed | 7 | |||
| Output voltage settling time | 5 | µs | ¼ to ¾ scale and ¾ to ¼ scale settling time to ±2 LSB, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 | 8 | |||
| Reference input impedance | 100 | kΩ | 8 | ||||
| Reference load current | -5 | 5 | mA | 9 | |||
| Junction-to-ambient thermal resistance | RθJA | 33.3 | °C/W | RTE (WQFN) 16 pins | 7 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 29.5 | °C/W | RTE (WQFN) 16 pins | 7 | ||
| Junction-to-board thermal resistance | RθJB | 7.3 | °C/W | RTE (WQFN) 16 pins | 7 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 0.9 | °C/W | RTE (WQFN) 16 pins | 7 |
CAD (KiCad official)
- Symbol:
DAC60504BRTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
dac60504brter-etched.step/dac60504brter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac60504brter.step/dac60504brter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (50 pp, sha256
c3866bfb0c308ae9, retrieved 2026-10-30, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).