component
DMN53D0L-7
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownDMN53D0L-7
Diodes Incorporated · MOSFETs · SOT-23
DMN53D0L-7 from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal; gate-source voltage is rated to ±20 V maximum, with threshold of 0.8 V to 1.5 V at ID = 250 µA, and an internal gate protection diode provides ESD protection. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, where continuous drain current is rated at 500 mA at TA = +25°C. |
| 3 | D | passive | Drain terminal; drain-source voltage is rated at 50 V maximum with 1.6 Ω RDS(ON) at VGS = 10 V and ID = 500 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-23 |
| Category | Transistors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 50 | V | VGS = 0V, ID = 250µA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 50V, VGS = 0V | 2 | ||
| Gate-Body Leakage | IGSS | 10 | µA | VGS = ±20V, VDS = 0V | 2 | ||
| Gate Threshold Voltage | VGS(th) | 0.8 | 1.5 | V | VDS = VGS, ID = 250µA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 1.6 | Ω | VGS = 10V, ID = 500mA | 2 | ||
| Static Drain-Source On-Resistance | RDS(ON) | 2.5 | Ω | VGS = 4.5V, ID = 200mA | 2 | ||
| Static Drain-Source On-Resistance | RDS(ON) | 4.5 | Ω | VGS = 2.5V, ID = 100mA | 2 | ||
| Source-Drain Diode Forward Voltage | VSD | 1.4 | V | VGS = 0V, IS = 500mA | 2 | ||
| Drain-Source Voltage | VDSS | 50 | V | TA = +25°C | 2 | ||
| Gate-Source Voltage | VGSS | -20 | 20 | V | TA = +25°C | 2 | |
| Drain Current | ID | 500 | mA | TA = +25°C, Note 5 | 2 | ||
| Total Power Dissipation (Note 6) | PD | 370 | mW | TA = +25°C, min recommended pad layout | 2 | ||
| Total Power Dissipation (Note 5) | PD | 540 | mW | TA = +25°C, 1inch square copper plate | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Thermal Resistance, Junction to Ambient (Note 6) | RθJA | 344 | C/W | TA = +25°C, min recommended pad layout | 2 | ||
| Thermal Resistance, Junction to Ambient (Note 5) | RθJA | 236 | C/W | TA = +25°C, 1inch square copper plate | 2 | ||
| Input Capacitance | Ciss | 46 | pF | VDS = 25V, VGS = 0V, f = 1.0MHz | 2 | ||
| Output Capacitance | Coss | 5.3 | pF | VDS = 25V, VGS = 0V, f = 1.0MHz | 2 | ||
| Reverse Transfer Capacitance | Crss | 4 | pF | VDS = 25V, VGS = 0V, f = 1.0MHz | 2 | ||
| Total Gate Charge | Qg | 0.6 | nC | VGS = 4.5V, VDS = 10V, ID = 250mA | 2 | ||
| Gate-Source Charge | Qgs | 0.2 | nC | VGS = 4.5V, VDS = 10V, ID = 250mA | 2 | ||
| Gate-Drain Charge | Qgd | 0.1 | nC | VGS = 4.5V, VDS = 10V, ID = 250mA | 2 | ||
| Turn-On Delay Time | tD(on) | 2.7 | ns | VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA | 2 | ||
| Turn-On Rise Time | tr | 2.5 | ns | VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA | 2 | ||
| Turn-Off Delay Time | tD(off) | 19 | ns | VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA | 2 | ||
| Turn-Off Fall Time | tf | 11 | ns | VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | • Terminals: Matte Tin Finish Annealed over Alloy 42 Leadframe (Lead-Free Plating). Solderable per MIL-STD-202, Method 208 | 1 |
CAD (land: KiCad; 3D: generated from the datasheet)
- Symbol:
DMN53D0L-7 - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23, generated on the KiCad land (body 1.3 x 2.9 mm, terminals on the pads, 0.975 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
dmn53d0l-7-etched.step/dmn53d0l-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmn53d0l-7.step/dmn53d0l-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
876fc767d750bee7, retrieved 2026-11-12, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).