DP83848MSQ from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IOVDD33	power_in	I/O 3.3-V supply; the device operates at VCC 3.3 V ±0.3 V.
2	TX_CLK	output	MII transmit clock output at 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25-MHz reference; unused in RMII mode.
3	TX_EN	input	MII transmit enable, active high, indicating valid data on TXD[3:0]; in RMII mode it indicates valid data on TXD[1:0].
4	TXD_0	input	MII transmit data bit 0, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); in RMII mode it is synchronous to the 50-MHz reference clock.
5	TXD_1	input	MII transmit data bit 1, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); in RMII mode it is synchronous to the 50-MHz reference clock.
6	TXD_2	input	MII transmit data bit 2, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); not used in RMII mode.
7	TXD_3	input	MII transmit data bit 3, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); not used in RMII mode.
8	RESERVED	unconnected	Reserved pin; must be left unconnected.
9	RESERVED	unconnected	Reserved pin; must be left unconnected.
10	RESERVED	unconnected	Reserved pin; must be left unconnected.
11	RD-	bidirectional	Differential receive input (PMD input pair) for 10BASE-T or 100BASE-TX; requires 3.3-V bias, and in Auto-MDIX mode this pair can serve as the transmit output.
12	RD+	bidirectional	Differential receive input (PMD input pair) for 10BASE-T or 100BASE-TX; requires 3.3-V bias, and in Auto-MDIX mode this pair can serve as the transmit output.
13	AGND	power_in	Analog ground.
14	TD-	bidirectional	Differential transmit output (PMD output pair) for 10BASE-T or 100BASE-TX; requires 3.3-V bias, and in Auto-MDIX mode this pair can serve as the receive input.
15	TD+	bidirectional	Differential transmit output (PMD output pair) for 10BASE-T or 100BASE-TX; requires 3.3-V bias, and in Auto-MDIX mode this pair can serve as the receive input.
16	PFBIN1	input	Power feedback input fed only from PFBOUT (pin 19), with a 0.1-µF capacitor close to the pin; do not supply power to this pin from any other source.
17	AGND	power_in	Analog ground.
18	AVDD33	power_in	Analog 3.3-V supply.
19	PFBOUT	output	Power feedback output; place parallel 10-µF (tantalum preferred) and 0.1-µF capacitors close to this pin and connect it to PFBIN1 (pin 16) and PFBIN2 (pin 30).
20	RBIAS	input	Bias resistor connection; a 4.87-kΩ 1% resistor must be connected from RBIAS to GND.
21	CLK_OUT	output	25-MHz clock output on the DP83848H/M/T (pin 21 is CLK_OUT on this variant, not LED_SPEED); the datasheet gives no further electrical limits for this pin.
22	LED_LINK/AN0	bidirectional	Link LED output (ON when link is good; in Mode 2 also blinks for transmit/receive activity); AN0 is a strap sampled at hardware reset, set with 2.2-kΩ resistors to GND or VCC and not to be tied directly.
23	RESET_N	input	Active-low reset with internal pullup; asserting it low for at least 1 µs forces a reset and re-latches all strap options.
24	MDIO	bidirectional	Management data I/O, bidirectional serial management data; requires a 1.5-kΩ pullup resistor.
25	MDC	input	Management data clock for the MDIO interface, maximum 25 MHz with no minimum clock rate.
26	IOVDD33	power_in	I/O 3.3-V supply; the device operates at VCC 3.3 V ±0.3 V.
27	X2	output	Crystal output for an external 25-MHz crystal resonator; must be left unconnected when an external CMOS oscillator drives X1.
28	X1	input	Primary clock input that must be a 25-MHz ±50 ppm source (crystal across X1/X2 or CMOS oscillator on X1); in RMII mode it is the 50-MHz ±50 ppm reference.
29	DGND	power_in	Digital ground.
30	PFBIN2	input	Power feedback input fed only from PFBOUT, with a 0.1-µF capacitor close to the pin; do not supply power to this pin from any other source.
31	RX_CLK	output	MII receive clock output at 25 MHz for 100 Mb/s or 2.5 MHz for 10 Mb/s; unused in RMII mode.
32	RX_DV/MII_MODE	bidirectional	MII receive data valid output (asserted when valid data is on RXD[3:0]); as a strap, high selects RMII mode and the internal pulldown defaults it to MII (0).
33	CRS/CRS_DV/LED_CFG	bidirectional	MII carrier sense output (or combined RMII carrier sense/receive data valid); as a strap it selects LED configuration mode, with default Mode 1 and a pullup.
34	RX_ER/MDIX_EN	bidirectional	MII receive error output (asserted synchronously to RX_CLK on invalid symbols in 100 Mb/s); as a strap, an external pulldown disables Auto-MDIX, which is enabled by default.
35	COL/PHYAD0	bidirectional	MII collision detect output (always 0 in full duplex); as a strap it is PHY address bit 0, latched at hardware reset, with weak internal pullup.
36	RXD_0/PHYAD1	bidirectional	MII receive data bit 0 (RMII RXD[0]), driven synchronously to RX_CLK (or X1 in RMII); as a strap it is PHY address bit 1 with weak internal pulldown.
37	RXD_1/PHYAD2	bidirectional	MII receive data bit 1 (RMII RXD[1]), driven synchronously to RX_CLK (or X1 in RMII); as a strap it is PHY address bit 2 with weak internal pulldown.
38	RXD_2/PHYAD3	bidirectional	MII receive data bit 2, valid when RX_DV is asserted; as a strap it is PHY address bit 3 with weak internal pulldown.
39	RXD_3/PHYAD4	bidirectional	MII receive data bit 3, valid when RX_DV is asserted; as a strap it is PHY address bit 4 with weak internal pulldown.
40	IOGND	power_in	I/O ground.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-40-EP(6x6)
Category	Communication Interface Chip/UART/485/232
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.5		4.2	V		10
DC input voltage	VIN	-0.5			V	Max printed as VCC + 0.5	10
DC output voltage	VOUT	-0.5			V	Max printed as VCC + 0.5	10
Max case temperature				147.7	°C		10
Max die temperature	TJ			150	°C		10
Storage temperature	Tstg	-65		150	°C		10
Human body model ESD	V(ESD)	-4000		4000	V	HBM, per ANSI/ESDA/JEDEC JS-001	10
Charged device model ESD	V(ESD)	-1000		1000	V	CDM, per JEDEC JESD22-C101	10
Supply voltage	VCC	-0.3	3.3	0.3	V	Printed 3.3 ±0.3 V	10
Ambient temperature, commercial DP83848J/M	TA	0		70	°C	Commercial - DP83848J/M	10
Input high voltage	VIH	2			V	Nominal VCC	11
Input low voltage	VIL			0.8	V		11
Input high current	IIH			10	µA	VIN = VCC	11
Input low current	IIL			10	µA	VIN = GND	11
Output low voltage	VOL			0.4	V	IOL = 4 mA	11
LED output low voltage	VledOL			0.4	V	IOL = 2.5 mA	11
Tri-state leakage	IOZ	-10		10	µA	VOUT = VCC	11
100M transmit voltage	VTPTD_100	0.95	1	1.05	V		11
100M transmit voltage symmetry	VTPTDsym	-2		2	%		11
10M transmit voltage	VTPTD_10	2.2	2.5	2.8	V		11
CMOS input capacitance	CIN1		5		pF		11
CMOS output capacitance	COUT1		5		pF		11
100BASE-TX signal detect turnon threshold	SDTHon		1000		mV diff pk-pk	PMD Input Pair	11
100BASE-TX signal detect turnoff threshold	SDTHoff		200		mV diff pk-pk	PMD Input Pair	11
10BASE-T receive threshold	VTH1		585		mV	PMD Input Pair	11
100BASE-TX full duplex supply current	Idd100		81		mA	IOUT = 0 mA, PMD Input Pair	11
10BASE-T full duplex supply current	Idd10		92		mA	10BASE-T (Full Duplex) supply	11
Junction-to-ambient thermal resistance	RθJA		31.7		°C/W	40-pin WQFN	10
Junction-to-case (top) thermal resistance	RθJC(top)		8.8		°C/W	40-pin WQFN	10
Junction-to-board thermal resistance	RθJB		40.5		°C/W	40-pin WQFN	10
Junction-to-top characterization parameter	ψJT		0.4		°C/W	40-pin WQFN	10
Junction-to-board characterization parameter	ψJB		10.5		°C/W	40-pin WQFN	10
Junction-to-case (bottom) thermal resistance	RθJC(bot)		5.5		°C/W	40-pin WQFN	10
Post power-up stabilization time before MDC preamble		167			ms	Register access, T2.1.1	11
Hardware configuration latch-in time from power up		167			ms	X1 clock stable at power up, T2.1.2	11
Hardware configuration pins transition to output drivers (power up)				50	ns	T2.1.3	11
Post RESET stabilization time before MDC preamble		3			µs	T2.2.1	11
Hardware configuration latch-in time from RESET deassertion		3			µs	T2.2.2	11
Hardware configuration pins transition to output drivers (reset)				50	ns	T2.2.3	11
RESET pulse width		1			µs	X1 clock stable during RESET low, T2.2.4	11
MDC to MDIO (output) delay		0		30	ns	T2.3.1	11
MDIO (input) to MDC setup time		10			ns	T2.3.2	11
MDIO (input) to MDC hold time		10			ns	T2.3.3	11
MDC frequency		2.5		25	MHz	T2.3.4	11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data.	46

CAD (KiCad official)

Symbol: DP83848MSQ
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: WQFN-40-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.8 mm tall, datasheet A, max). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
3D model files: dp83848msq-etched.step / dp83848msq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83848msq.step / dp83848msq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (87 pp, sha256 14b0911cb23ad857, retrieved 2026-11-12, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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