AD7324BRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CS	input	Active-low chip select that initiates conversions and frames the serial data transfer.
2	DIN	input	Serial data input for writing to the on-chip registers, clocked in on the falling edge of SCLK.
3	DGND	power_in	Digital ground reference for all digital circuitry; DGND and AGND must not be more than 0.3 V apart, even transiently.
4	AGND	power_in	Analog ground reference for all analog circuitry, analog inputs and external reference; must be within 0.3 V of DGND.
5	REFIN/OUT	bidirectional	Reference input/output: provides the 2.5 V internal reference (needs a 680 nF capacitor) or accepts an external reference, which is the power-up default.
6	VSS	power_in	Negative supply voltage for the analog input section.
7	VIN0	input	Analog input 0, multiplexed into the track-and-hold; configurable as single-ended, true differential or pseudo differential with ranges of ±10 V, ±5 V, ±2.5 V or 0 V to +10 V.
8	VIN1	input	Analog input 1, multiplexed into the track-and-hold; configurable as single-ended, true differential or pseudo differential with ranges of ±10 V, ±5 V, ±2.5 V or 0 V to +10 V.
9	VIN3	input	Analog input 3, multiplexed into the track-and-hold; configurable as single-ended, true differential or pseudo differential with ranges of ±10 V, ±5 V, ±2.5 V or 0 V to +10 V.
10	VIN2	input	Analog input 2, multiplexed into the track-and-hold; configurable as single-ended, true differential or pseudo differential with ranges of ±10 V, ±5 V, ±2.5 V or 0 V to +10 V.
11	VDD	power_in	Positive supply voltage for the analog input section.
12	VCC	power_in	Analog supply for the ADC core, 2.7 V to 5.25 V (specifications apply from 4.75 V to 5.25 V), decoupled to AGND.
13	VDRIVE	power_in	Logic power supply input that sets the interface voltage, decoupled to DGND and not exceeding VCC by more than 0.3 V.
14	DOUT	output	Serial data output, MSB first, clocked out on the falling edge of SCLK; 16 SCLKs are required to access the data (leading zero, 2 channel ID bits, sign bit, 12 data bits).
15	DGND	power_in	Digital ground reference for all digital circuitry; DGND and AGND must not be more than 0.3 V apart, even transiently.
16	SCLK	input	Serial clock logic input for accessing data, also used as the clock source for the conversion process.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	ADC/DAC/Data Conversion
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Offset Error (single-ended/pseudo differential)		-4		9	LSB	Single-ended/pseudo differential mode	4
Offset Error (differential)		-7		10	LSB	Differential mode	4
Integral Nonlinearity (SE/pseudo diff, LSB=FSR/8192)		-0.7		1.2	LSB	Single-ended/pseudo differential mode (LSB = FSR/8192)	3
Differential Nonlinearity (differential)		-0.9		1.5	LSB	Differential mode; guaranteed no missing codes to 13 bits	4
Differential Nonlinearity (SE/pseudo diff, LSB=FSR/8192)		-0.7		1	LSB	Single-ended/pseudo differential mode (LSB = FSR/8192)	4
Offset Error Match (SE/pseudo diff)		-0.6		0.6	LSB	Single-ended/pseudo differential mode	4
Offset Error Match (differential)		-0.5		0.5	LSB	Differential mode	4
Gain Error (SE/pseudo diff)		-8		8	LSB	Single-ended/pseudo differential mode	4
Gain Error (differential)		-14		14	LSB	Differential mode	4
Positive Full-Scale Error (SE/pseudo diff)		-4		4	LSB	Single-ended/pseudo differential mode	4
Positive Full-Scale Error (differential)		-7		7	LSB	Differential mode	4
Bipolar Zero Error (SE/pseudo diff)		-8.5		8.5	LSB	Single-ended/pseudo differential mode	4
Bipolar Zero Error (differential)		-7.5		7.5	LSB	Differential mode	4
Negative Full-Scale Error (SE/pseudo diff)		-4		4	LSB	Single-ended/pseudo differential mode	4
Negative Full-Scale Error (differential)		-6		6	LSB	Differential mode	4
DC Leakage Current		-80		80	nA	VIN = VDD or VSS	4
Reference Input Voltage Range		2.5		3	V		4
Reference Input DC Leakage Current		-1		1	µA		4
Reference Output Voltage Error at 25°C		-5		5	mV		4
Reference Output Voltage TMIN to TMAX		-10		10	mV		5
Input High Voltage	VINH	2.4			V		5
Input Low Voltage	VINL			0.8	V	VCC = 4.75 V to 5.25 V	5
Input Low Voltage	VINL			0.4	V	VCC = 2.7 V to 3.6 V	5
Logic Input Current	IIN	-1		1	µA	VIN = 0 V or VDRIVE	5
Output Low Voltage	VOL			0.4	V	ISINK = 200 µA	5
Floating-State Leakage Current		-1		1	µA		5
Supply Voltage VDD	VDD	12		16.5	V	See Table 6	5
Supply Voltage VSS	VSS	-12		-16.5	V	See Table 6	5
Supply Voltage VCC	VCC	2.7		5.25	V	See Table 6; typical specifications for VCC < 4.75 V	5
Supply Voltage VDRIVE	VDRIVE	2.7		5.25	V		5
Power Dissipation, Normal Mode (Operational)				31	mW	VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V	6
Power Dissipation, Full Shutdown Mode				38.25	µW	VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V	6
Serial Clock Frequency (min)	fSCLK	50			kHz	VCC < 4.75 V and VCC = 4.75 V to 5.25 V	7
Serial Clock Frequency (max, VCC = 4.75 V to 5.25 V)	fSCLK			20	MHz	VCC = 4.75 V to 5.25 V	7
Serial Clock Frequency (max, VCC < 4.75 V)	fSCLK			14	MHz	VCC < 4.75 V	7
Quiet Time	tQUIET	60			ns	VCC = 4.75 V to 5.25 V; time between end of serial read and next falling edge of CS	7
CS Pulse Width	t1	5			ns	VCC = 4.75 V to 5.25 V	7
CS to SCLK Setup Time, bipolar ranges	t2	20			ns	VCC = 4.75 V to 5.25 V; ±10 V, ±5 V, ±2.5 V	7
Delay from CS until DOUT three-state disabled	t3			14	ns	VCC = 4.75 V to 5.25 V	7
Data access time after SCLK falling edge	t4			43	ns	VCC = 4.75 V to 5.25 V	7
DIN setup time	t9	4			ns	Prior to SCLK falling edge	7
DIN hold time	t10	2			ns	After SCLK falling edge	7
Power-up time from full shutdown/autoshutdown, internal reference	tPOWER-UP			500	µs	Internal reference	7
VDD to AGND, DGND	VDD	-0.3		16.5	V	TA = 25°C	8
VSS to AGND, DGND	VSS	-16.5		0.3	V	TA = 25°C	8
VCC to AGND, DGND	VCC	-0.3		7	V	TA = 25°C	8
VDRIVE to AGND, DGND	VDRIVE	-0.3		7	V	TA = 25°C	8
AGND to DGND		-0.3		0.3	V	TA = 25°C	8
Digital Input Voltage to DGND		-0.3		7	V	TA = 25°C	8
Input Current to Any Pin Except Supplies		-10		10	mA	TA = 25°C	8
Operating Temperature Range		-40		85	°C		8
Storage Temperature Range		-65		150	°C		8
Junction Temperature				150	°C		8
Thermal Impedance Junction-to-Ambient	θJA		150.4		°C/W	TSSOP package	8
Thermal Impedance Junction-to-Case	θJC		27.6		°C/W	TSSOP package	8
Reference Output Voltage			2.5		V		4
Reference Temperature Coefficient			25		ppm/°C		5

CAD (KiCad official)

Symbol: AD7324BRUZ-REEL7
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad7324bruz-reel7-etched.step / ad7324bruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7324bruz-reel7.step / ad7324bruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (36 pp, sha256 53cb319d2c2356f3, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7324BRUZ-REEL7

Verified AD7324BRUZ-REEL7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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