MSP430F67641AIPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SD0P0	input	Sigma-Delta ADC0 channel 0 positive analog input. Powered from AVCC.
2	SD0N0	input	Sigma-Delta ADC0 channel 0 negative analog input. Powered from AVCC.
3	SD1P0	input	Sigma-Delta ADC1 channel 0 positive analog input. Powered from AVCC.
4	SD1N0	input	Sigma-Delta ADC1 channel 0 negative analog input. Powered from AVCC.
5	SD2P0	input	Sigma-Delta ADC2 channel 0 positive analog input. Powered from AVCC.
6	SD2N0	input	Sigma-Delta ADC2 channel 0 negative analog input. Powered from AVCC.
7	VREF	input	Sigma-Delta ADC reference voltage input.
8	AVSS	power_in	Analog ground reference for AVCC and analog circuitry.
9	AVCC	power_in	Analog supply voltage for the ADCs and analog reference (1.8 V to 3.6 V).
10	VASYS	power_in	Analog system supply pin - part of the internal supply-management network for analog domains.
11	P9.1/A5	bidirectional	GPIO P9.1 (LVCMOS, DVCC-powered) with muxed 10-bit ADC input A5 (analog, AVCC-powered). Reset state: high-Z, pulls disabled.
12	P9.2/A4	bidirectional	GPIO P9.2 with muxed 10-bit ADC input A4.
13	P9.3/A3	bidirectional	GPIO P9.3 with muxed 10-bit ADC input A3.
14	P1.0/PM_TA0.0/VeREF-/A2	bidirectional	GPIO P1.0 with mappable secondary Timer_A0 CC0 (PM_TA0.0), plus muxed external ADC negative reference input (VeREF-) and 10-bit ADC input A2.
15	P1.1/PM_TA0.1/VeREF+/A1	bidirectional	GPIO P1.1 with mappable PM_TA0.1, external ADC positive reference input (VeREF+) and 10-bit ADC input A1.
16	P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0	bidirectional	GPIO P1.2 with mappable USCI_A0 UART RXD or SPI SOMI, and 10-bit ADC input A0.
17	P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03	bidirectional	GPIO P1.3 with mappable USCI_A0 UART TXD or SPI SIMO, and LCD external contrast resistor tap R03 (analog).
18	AUXVCC2	power_in	Auxiliary supply input 2 for automatic power-switching between main supply and backup sources.
19	AUXVCC1	power_in	Auxiliary supply input 1 for automatic power-switching between main supply and backup sources.
20	VDSYS	power_in	Digital system supply pin. Must be connected externally on the board to DVSYS for proper operation.
21	DVCC	power_in	Digital supply voltage (1.8 V to 3.6 V) for the digital core, I/O, and LVCMOS buffers.
22	DVSS	power_in	Digital ground reference for DVCC and digital I/O.
23	VCORE	passive	Core LDO decoupling pin - connect an external bypass capacitor to DVSS; do not drive.
24	XIN	input	32.768 kHz LF crystal oscillator input terminal.
25	XOUT	output	32.768 kHz LF crystal oscillator output terminal.
26	AUXVCC3	power_in	Dedicated auxiliary supply for the RTC (allows RTC operation from a backup source such as a coin cell).
27	P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13	bidirectional	GPIO P1.4 with mappable USCI_A1 UART RXD or SPI SOMI, plus LCD external reference input (LCDREF) and LCD contrast resistor tap R13.
28	P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23	bidirectional	GPIO P1.5 with mappable USCI_A1 UART TXD or SPI SIMO, and LCD contrast resistor tap R23.
29	LCDCAP/R33	bidirectional	LCD charge-pump capacitor pin (analog); alternate LCD contrast resistor tap R33. Connect to DVSS if the LCD is not used.
30	P8.4/TA1.0	bidirectional	GPIO P8.4 with Timer_A1 CC0 (TA1.0) capture/compare alt function.
31	P8.5/TA1.1	bidirectional	GPIO P8.5 with Timer_A1 CC1 (TA1.1) capture/compare alt function.
32	COM0	output	LCD common (backplane) output 0.
33	COM1	output	LCD common (backplane) output 1.
34	COM2	output	LCD common (backplane) output 2.
35	COM3	output	LCD common (backplane) output 3.
36	P1.6/PM_UCA0CLK/COM4	bidirectional	GPIO P1.6 with mappable USCI_A0 clock (PM_UCA0CLK) and LCD common output COM4.
37	P1.7/PM_UCB0CLK/COM5	bidirectional	GPIO P1.7 with mappable USCI_B0 clock (PM_UCB0CLK) and LCD common output COM5.
38	P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6	bidirectional	GPIO P2.0 with muxed USCI_B0 SPI SOMI or I2C SCL, and LCD common output COM6.
39	P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7	bidirectional	GPIO P2.1 with muxed USCI_B0 SPI SIMO or I2C SDA, and LCD common output COM7.
40	P8.6/TA2.0	bidirectional	GPIO P8.6 with Timer_A2 CC0 (TA2.0) capture/compare alt function.
41	P8.7/TA2.1	bidirectional	GPIO P8.7 with Timer_A2 CC1 (TA2.1) capture/compare alt function.
42	P9.0/TACLK/RTCCLK	bidirectional	GPIO P9.0 with Timer_A external clock input (TACLK) and RTC clock output (RTCCLK).
43	P2.2/PM_UCA2RXD/PM_UCA2SOMI	bidirectional	GPIO P2.2 with mappable USCI_A2 UART RXD or SPI SOMI.
44	P2.3/PM_UCA2TXD/PM_UCA2SIMO	bidirectional	GPIO P2.3 with mappable USCI_A2 UART TXD or SPI SIMO.
45	P2.4/PM_UCA1CLK	bidirectional	GPIO P2.4 with mappable USCI_A1 clock (PM_UCA1CLK).
46	P2.5/PM_UCA2CLK	bidirectional	GPIO P2.5 with mappable USCI_A2 clock (PM_UCA2CLK).
47	P2.6/PM_TA1.0	bidirectional	GPIO P2.6 with mappable Timer_A1 CC0 (PM_TA1.0).
48	P2.7/PM_TA1.1	bidirectional	GPIO P2.7 with mappable Timer_A1 CC1 (PM_TA1.1).
49	P3.0/PM_TA2.0/BSL_TX	bidirectional	GPIO P3.0 with mappable Timer_A2 CC0 (PM_TA2.0) and Bootloader UART TX (BSL_TX).
50	P3.1/PM_TA2.1/BSL_RX	bidirectional	GPIO P3.1 with mappable Timer_A2 CC1 (PM_TA2.1) and Bootloader UART RX (BSL_RX).
51	P3.2/PM_TACLK/PM_RTCCLK	bidirectional	GPIO P3.2 with mappable Timer_A external clock input (PM_TACLK) and RTC clock output (PM_RTCCLK).
52	P3.3/PM_TA0.2	bidirectional	GPIO P3.3 with mappable Timer_A0 CC2 (PM_TA0.2).
53	P3.4/PM_SDCLK/S39	bidirectional	GPIO P3.4 with mappable Sigma-Delta external clock (PM_SDCLK) and LCD segment output S39.
54	P3.5/PM_SD0DIO/S38	bidirectional	GPIO P3.5 with mappable SD24_B modulator 0 digital I/O and LCD segment output S38.
55	P3.6/PM_SD1DIO/S37	bidirectional	GPIO P3.6 with mappable SD24_B modulator 1 digital I/O and LCD segment output S37.
56	P3.7/PM_SD2DIO/S36	bidirectional	GPIO P3.7 with mappable SD24_B modulator 2 digital I/O and LCD segment output S36.
57	P4.0/S35	bidirectional	GPIO P4.0 with LCD segment output S35.
58	P4.1/S34	bidirectional	GPIO P4.1 with LCD segment output S34.
59	P4.2/S33	bidirectional	GPIO P4.2 with LCD segment output S33.
60	P4.3/S32	bidirectional	GPIO P4.3 with LCD segment output S32.
61	P4.4/S31	bidirectional	GPIO P4.4 with LCD segment output S31.
62	P4.5/S30	bidirectional	GPIO P4.5 with LCD segment output S30.
63	P4.6/S29	bidirectional	GPIO P4.6 with LCD segment output S29.
64	P4.7/S28	bidirectional	GPIO P4.7 with LCD segment output S28.
65	P5.0/S27	bidirectional	GPIO P5.0 with LCD segment output S27.
66	P5.1/S26	bidirectional	GPIO P5.1 with LCD segment output S26.
67	P5.2/S25	bidirectional	GPIO P5.2 with LCD segment output S25.
68	P5.3/S24	bidirectional	GPIO P5.3 with LCD segment output S24.
69	P5.4/S23	bidirectional	GPIO P5.4 with LCD segment output S23.
70	P5.5/S22	bidirectional	GPIO P5.5 with LCD segment output S22.
71	P5.6/S21	bidirectional	GPIO P5.6 with LCD segment output S21.
72	P5.7/S20	bidirectional	GPIO P5.7 with LCD segment output S20.
73	P6.0/S19	bidirectional	GPIO P6.0 with LCD segment output S19.
74	DVSYS	power_in	Digital system supply pin - must be tied externally on the board to VDSYS for proper device operation.
75	DVSS	power_in	Digital ground reference (second bond) for DVCC and digital I/O.
76	P6.1/S18	bidirectional	GPIO P6.1 with LCD segment output S18.
77	P6.2/S17	bidirectional	GPIO P6.2 with LCD segment output S17.
78	P6.3/S16	bidirectional	GPIO P6.3 with LCD segment output S16.
79	P6.4/S15	bidirectional	GPIO P6.4 with LCD segment output S15.
80	P6.5/S14	bidirectional	GPIO P6.5 with LCD segment output S14.
81	P6.6/S13	bidirectional	GPIO P6.6 with LCD segment output S13.
82	P6.7/S12	bidirectional	GPIO P6.7 with LCD segment output S12.
83	P7.0/S11	bidirectional	GPIO P7.0 with LCD segment output S11.
84	P7.1/S10	bidirectional	GPIO P7.1 with LCD segment output S10.
85	P7.2/S9	bidirectional	GPIO P7.2 with LCD segment output S9.
86	P7.3/S8	bidirectional	GPIO P7.3 with LCD segment output S8.
87	P7.4/S7	bidirectional	GPIO P7.4 with LCD segment output S7.
88	P7.5/S6	bidirectional	GPIO P7.5 with LCD segment output S6.
89	P7.6/S5	bidirectional	GPIO P7.6 with LCD segment output S5.
90	P7.7/S4	bidirectional	GPIO P7.7 with LCD segment output S4.
91	P8.0/S3	bidirectional	GPIO P8.0 with LCD segment output S3.
92	P8.1/S2	bidirectional	GPIO P8.1 with LCD segment output S2.
93	P8.2/S1	bidirectional	GPIO P8.2 with LCD segment output S1.
94	P8.3/S0	bidirectional	GPIO P8.3 with LCD segment output S0.
95	TEST/SBWTCK	input	Test mode select - enables digital I/O on JTAG pins. Also serves as the Spy-Bi-Wire input clock (SBWTCK).
96	PJ.0/SMCLK/TDO	bidirectional	GPIO PJ.0 with SMCLK clock output and JTAG test data output (TDO).
97	PJ.1/MCLK/TDI/TCLK	bidirectional	GPIO PJ.1 with MCLK clock output and JTAG test data input / test clock input (TDI/TCLK).
98	PJ.2/ADC10CLK/TMS	bidirectional	GPIO PJ.2 with 10-bit ADC clock output (ADC10CLK) and JTAG test mode select (TMS).
99	PJ.3/ACLK/TCK	bidirectional	GPIO PJ.3 with ACLK clock output and JTAG test clock (TCK).
100	RST/NMI/SBWTDIO	bidirectional	Active-low reset input (RST), non-maskable interrupt input (NMI), and Spy-Bi-Wire bidirectional data I/O (SBWTDIO). Reset default: high-Z input with pullup enabled.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

Ordering variants

Same part, different packaging or reel option.

MSP430F67641AIPZR
MSP430F67641AIPZRIPN
MSP430F67641AIPZRIPNR

CAD (KiCad official)

Symbol: MSP430F67641AIPZR
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 4f4b60167e8688ea, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF