component
RT6362GSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT6362GSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT6362GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap capacitor connection node to supply the high-side gate driver; connect a 0.1µF ceramic capacitor between this pin and the SW pin. |
| 2 | VIN | power_in | Power input with an input voltage range of 4V to 60V; connect a suitable input capacitor between this pin and GND, usually two 2.2µF or larger ceramic capacitors with one typical capacitance of 4.7µF. |
| 3 | EN | input | Enable control pin with internal pull-up current source; floating or a logic-high (≥1.25V) enables the converter, and a logic-low forces the device into shutdown mode. |
| 4 | RT/SYNC | input | Frequency setting and external synchronization input; connect a resistor from this pin to GND to set the switching frequency, or tie it to a clock source to synchronize to an external frequency. |
| 5 | FB | input | Output voltage sense input through a resistive divider, with a feedback reference voltage of 0.8V typically. |
| 6 | COMP | passive | Compensation node; external compensation elements connected to this pin stabilize the control loop. |
| 7 | GND | power_in | Ground; provides the ground return path for the control circuitry. |
| 8 | SW | power_out | Switch node that supplies power to the output; connect the output LC filter from SW to the output load. |
| 9 | PAD | passive | Exposed pad is internally unconnected and must be soldered to a large PCB copper area for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Operating Voltage | VIN | 4 | 60 | V | After soft-start is finished | 11 | |
| VIN Under-Voltage Lockout Threshold (rising) | VUVLOH | 4.1 | 4.3 | 4.5 | V | VIN rising | 11 |
| VIN Under-Voltage Lockout Threshold (falling) | VUVLOL | 3.8 | 3.9 | 4 | V | VIN falling | 11 |
| Shutdown Current | ISHDN | 1.3 | 4 | μA | VEN = 0V | 11 | |
| Quiescent Current | IQ | 90 | 110 | μA | VEN = 2V, VFB = 0.83V, not switching | 11 | |
| Enable Threshold Voltage | VTH_EN | 1.15 | 1.25 | 1.36 | V | 11 | |
| Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | 11 | |
| High-Side Switch On-Resistance | RDS(ON)_H | 150 | 260 | mΩ | VIN = 12V, VBOOT-VSW = 5V | 11 | |
| Current Limit | ILIM | 3.825 | 4.5 | 5.175 | A | fSW = 580kHz, VOUT = 5V | 11 |
| Minimum On-Time | tON_MIN | 100 | 130 | ns | IOUT = 1A | 12 | |
| Switching Frequency 1 | fSW1 | 85 | 100 | 115 | kHz | RRT/SYNC = 1.2M | 12 |
| Switching Frequency 2 | fSW2 | 520 | 580 | 640 | kHz | RRT/SYNC = 200k | 12 |
| Switching Frequency 3 | fSW3 | 2250 | 2500 | 2750 | kHz | RRT/SYNC = 44.2k | 12 |
| SYNC Frequency Range | fSYNC | 0.3 | 2.2 | MHz | External clock | 12 | |
| SYNC Threshold Voltage (high) | VIH_SYNC | 1.9 | 2.2 | V | 12 | ||
| SYNC Threshold Voltage (low) | VIL_SYNC | 0.5 | 0.7 | V | 12 | ||
| Soft-Start Period (10% to 90%) | tSS | 1.4 | 2 | 2.6 | ms | 10% to 90%, RT6362GSP | 12 |
| Input Voltage Absolute Maximum | VIN | -0.3 | 65 | V | Supply voltage | 10 | |
| Enable Voltage Absolute Maximum | EN | -0.3 | 65 | V | 10 | ||
| Switch Voltage Absolute Maximum | SW | -0.6 | 65 | V | 10 | ||
| Switch Voltage Absolute Maximum (transient) | SW | -5 | 70 | V | t ≤ 100ns | 10 | |
| Switch Voltage Absolute Maximum (transient) | SW | -7 | 70 | V | t ≤ 5ns | 10 | |
| BOOT to SW Voltage Absolute Maximum | BOOT-SW | -0.3 | 6 | V | 10 | ||
| All Other Pins Voltage Absolute Maximum | -0.3 | 6 | V | All other pins | 10 | ||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 10 | |||
| Junction Temperature | TJ | 150 | °C | 10 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 10 | ||
| Supply Input Voltage | VIN | 4 | 60 | V | 10 | ||
| Output Voltage | VOUT | 0.8 | V | Upper limit is VIN | 10 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 10 | ||
| Junction-to-ambient thermal resistance (JEDEC standard), SOP-8 (Exposed pad) | θJA | 31.8 | °C/W | JEDEC standard | 10 | ||
| Junction-to-case (top) thermal resistance, SOP-8 (Exposed pad) | θJC(Top) | 74.1 | °C/W | 10 | |||
| Junction-to-case (bottom) thermal resistance, SOP-8 (Exposed pad) | θJC(Bottom) | 4.9 | °C/W | 10 | |||
| Junction-to-ambient thermal resistance (specific EVB), SOP-8 (Exposed pad) | θJA(EVB) | 31.4 | °C/W | Specific EVB | 10 | ||
| Junction-to-top characterization parameter, SOP-8 (Exposed pad) | ψJT | 5.1 | °C/W | 10 | |||
| Junction-to-board characterization parameter, SOP-8 (Exposed pad) | ψJB | 14.7 | °C/W | 10 |
CAD (KiCad official)
- Symbol:
RT6362GSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt6362gsp-etched.step/rt6362gsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6362gsp.step/rt6362gsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (38 pp, sha256
b92f7b4ec3be0cd1, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).