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README

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VP3481DNG10

VIVA(昱盛) · DC-DC Converters · TDFN-10-EP(3x3)

VP3481DNG10 from VIVA(昱盛), in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ISEN input Current sense input: an external resistor in series with ground measures the voltage drop, and the current limit activates when the voltage between ISEN and ground exceeds 230 mV.
2 UVLO input Undervoltage lockout input compared against the internal 1.43 V reference, where a resistor divider sets the enable and disable thresholds and the 4.5 μA UVLO source current sets the hysteresis.
3 COMP input Error amplifier compensation pin, where an RC or C network provides proper loop compensation.
4 FB input Output feedback input, regulated to the internal 1.275 V reference through an external resistor divider, with overvoltage protection triggered when the voltage rises to VFB + VOVP.
5 AGND power_in Analog ground, to be connected to the exposed pad.
6 FADJ input Frequency adjust, synchronization and shutdown pin: a resistor to ground sets the oscillator frequency between 100 kHz and 1 MHz, an external clock synchronizes the controller, and holding the pin high for 30 µs or more shuts the device down.
7 PVSS power_in Power ground, to be connected to the exposed pad.
8 GATE output Gate drive output that connects to the gate of the external N-channel MOSFET, with a maximum gate swing of 5.2 V when VIN is 5.8 V or higher.
9 VREG power_out Internal drive supply output that requires a bypass capacitor of 0.47 μF to 4.7 μF to ground and must not be biased by an external power source.
10 IN power_in Power supply input, with a recommended supply voltage range of 2.97 V to 40 V and an absolute maximum of 42 V.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer VIVA(昱盛)
Package TDFN-10-EP(3x3)
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Feedback voltage (-40℃<TJ<125℃) VFB 1.236 1.313 V VCOMP=1.4V, 3V<VIN<40V, -40℃<TJ<125℃ 4
Under voltage lockout (ramp down) VUVLO 1.345 1.517 V Ramp down 4
UVLO shutdown voltage VUVLOSD 0.55 0.7 0.82 V 4
Oscillation frequency (-40℃<TJ<125℃) fOSC 0.125 0.2 MHz RFADJ=150kΩ, -40℃<TJ<125℃ 4
Voltage load regulation ΔVLOAD -0.5 0.5 %/A IEAO Source/Sink 4
Current sense threshold voltage (-40℃<TJ<125℃) VSENSE 120 200 mV VIN=12V, -40℃<TJ<125℃ 4
Overload current limit sense voltage (-40℃<TJ<125℃) VSC 160 350 mV VIN=12V, -40℃<TJ<125℃ 4
Output overvoltage protection VOVP 26 85 135 mV VCOMP=1.4V 5
Output overvoltage protection hysteresis VOVP(HYS) 28 70 106 mV VCOMP=1.4V 5
Error amplifier output current, source (-40℃<TJ<125℃) IEAO 470 950 μA Source, VCOMP = 1.4V, VFB = 0V, -40℃<TJ<125℃ 5
Error amplifier output current, sink (-40℃<TJ<125℃) IEAO 30 105 μA Sink, VCOMP = 1.4V, VFB = 1.4V, -40℃<TJ<125℃ 5
Error amplifier output voltage, upper limit (-40℃<TJ<125℃) VEAO 2.4 2.95 V Upper Limit: VFB=0V, COMP pin floating -40℃<TJ<125℃ 5
Error amplifier output voltage, lower limit (-40℃<TJ<125℃) VEAO 0.32 0.9 V Lower Limit: VFB=1.4V -40℃<TJ<125℃ 5
Soft start delay tSS 8.7 15 21.3 mS VFB = 1.2V, COMP pin floating 5
Supply voltage range (absolute maximum) VIN -0.3 42 V 3
Low voltage range (COMP/UVLO/FB/FADJ/GATE) VLV -0.3 6 V 3
Regulator output pin range VCC(VREG) -0.3 5 V 3
Current sense pin range VISEN -0.4 0.6 V 3
Junction temperature maximum TJMAX 150 oC 3
Storage temperature range TSTG -65 150 oC 3
Electrostatic discharge, human body model 2 kV 3
Supply voltage VIN 2.97 40 V 3
Switching frequency range fOSC 0.1 1 MHz 3
Operating junction range TJ -40 125 oC 3
Feedback voltage (25℃, 3V<VIN<40V) VFB 1.275 V VCOMP=1.4V, 3V<VIN<40V 4
Quiescent current in shutdown mode IQ 10 μA VFADJ=3V, VIN=12V 4
Quiescent current in shutdown mode (-40℃<TJ<125℃) IQ 15 μA VIN=12V, -40℃<TJ<125℃ 4
Quiescent current in shutdown mode IQ 5 μA VIN=5V 4
Quiescent current in shutdown mode (-40℃<TJ<125℃) IQ 10 μA VIN=5V, -40℃<TJ<125℃ 4
UVLO source current IUVLO 4.5 μA Enabled 4
COMP pin voltage VCOMP 1 V VFB=1.275V 4
High-side switch RDS(ON) RDS(ON) 4 Ω VIN=5V, IGATE=0.2A 4
Low-side switch RDS(ON) RDS(ON) 2 Ω VIN=5V, IGATE=0.2A 4
Error amplifier voltage gain AVOL 60 V/V VCOMP=1.4V, IEAO=100μA 4
Error amplifier transconductance gM 430 μ℧ VCOMP=1.4V 4
Maximum GATE driving swing (VIN≥5.8V) VGATE 5.2 V VIN≥5.8V 4
Oscillation frequency fOSC 0.146 MHz RFADJ=150kΩ 4
Supply current ISUPPLY 3.3 mA RFADJ=150kΩ 4
Supply current (-40℃<TJ<125℃) ISUPPLY 5 mA RFADJ=150kΩ, -40℃<TJ<125℃ 4
Maximum duty cycle DMAX 85 % RFADJ=150kΩ 4
Voltage line regulation ΔVLINE 0.02 %/V 3V<VIN<40V 4
Minimum on-time tMIN(ON) 571 nS 4
Current sense threshold voltage VSENSE 160 mV VIN=12V 4
Overload current limit sense voltage VSC 200 mV VIN=12V 4
Internal compensation ramp VSL 90 mV 4
Error amplifier output current, source IEAO 650 μA Source, VCOMP = 1.4V, VFB = 0V 5
Error amplifier output current, sink IEAO 57 μA Sink, VCOMP = 1.4V, VFB = 1.4V 5
Error amplifier output voltage, upper limit VEAO 2.65 V Upper Limit: VFB=0V, COMP pin floating 5
Error amplifier output voltage, lower limit VEAO 0.65 V Lower Limit: VFB=1.4V 5
Shutdown signal threshold on FADJ pin, high level (SD) VSD 1.26 V Output=High Level (SD) 5
Shutdown signal threshold on FADJ pin, high level (SD) (-40℃<TJ<125℃) VSD 1.4 V Output=High Level (SD), -40℃<TJ<125℃ 5
Shutdown signal threshold on FADJ pin, low level (EN) VSD 0.63 V Output=Low Level (EN) 5
Shutdown signal threshold on FADJ pin, low level (EN) (-40℃<TJ<125℃) VSD 0.4 V Output=Low Level (EN), -40℃<TJ<125℃ 5
Shutdown pin current ISD 10 μA FADJ pin VSD=0V 5
GATE pin rising time tR 18 nS Cgs = 3000pF, VGATE = 0V to 3V 5
GATE pin falling time tF 12 nS Cgs = 3000pF, VGATE = 3V to 0V 5
Thermal shutdown TSD 175 ℃ 5
Thermal resistance (Junction to Case (top)) θJC(top) 54 oC/W 3
Thermal resistance (Junction to Air) θJA 49 oC/W 3
Thermal resistance (Junction to Board) θJB 21 oC/W 3

CAD (KiCad official)

  • Symbol: VP3481DNG10
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: vp3481dng10-etched.step / vp3481dng10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vp3481dng10.step / vp3481dng10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VIVA(昱盛) datasheet (19 pp, sha256 3ef87c4438cd76a5, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF