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5PB1108PGGI
Public Made by Adomby adom
RENESAS Clock Buffers/Drivers/Distributions, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdown5PB1108PGGI
RENESAS · Clock Buffers/Drivers/Distributions · TSSOP-16
5PB1108PGGI from RENESAS, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLKIN | input | LVCMOS clock input, 3.3V tolerant, with input voltage rated -0.4V to 3.465V. |
| 2 | 1G | input | Clock output enable: outputs Yn are held low when 1G is low and follow CLKIN when 1G is high. |
| 3 | Y0 | output | LVCMOS clock output 0 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
| 4 | GND | power_in | Ground. |
| 5 | VDD | power_in | Power supply, 1.71V to 3.465V relative to GND. |
| 6 | Y4 | output | LVCMOS clock output 4 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
| 7 | GND | power_in | Ground. |
| 8 | Y6 | output | LVCMOS clock output 6 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
| 9 | Y7 | output | LVCMOS clock output 7 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
| 10 | VDD | power_in | Power supply, 1.71V to 3.465V relative to GND. |
| 11 | Y5 | output | LVCMOS clock output 5 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
| 12 | GND | power_in | Ground. |
| 13 | Y2 | output | LVCMOS clock output 2 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
| 14 | VDD | power_in | Power supply, 1.71V to 3.465V relative to GND. |
| 15 | Y3 | output | LVCMOS clock output 3 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
| 16 | Y1 | output | LVCMOS clock output 1 with integrated serial termination for a 50Ω channel, rated -0.4V to VDD+0.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TSSOP-16 |
| Category | Clock And Timing |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3.8 | V | 5 | |||
| Output Enable and All Outputs | -0.4 | V | -0.4 V to VDD + 0.5 V | 5 | |||
| Input Voltage, CLKIN | -0.4 | 3.465 | V | 5 | |||
| Storage Temperature | -65 | 150 | C | 5 | |||
| Junction Temperature | 125 | C | 5 | ||||
| Soldering Temperature | 260 | C | 5 | ||||
| Ambient Operating Temperature (Industrial) | -40 | 85 | C | 5 | |||
| Power Supply Voltage | VDD | 1.71 | 3.465 | V | measured in respect to GND | 5 | |
| Thermal Resistance Junction to Ambient, 16-TSSOP | ΘJA | 80.9 | °C/W | still air | 6 | ||
| Thermal Resistance Junction to Case, 16-TSSOP | ΘJC | 43.3 | °C/W | still air | 6 | ||
| Thermal Resistance Junction to Board, 16-TSSOP | ΘJB | 60.1 | °C/W | still air | 6 | ||
| Operating Voltage, 1.8V | VDD | 1.71 | 1.8 | 1.89 | V | VDD = 1.8V ±5%, Industrial | 7 |
| Input High Voltage, 1G, 1.8V | VIH | 1.6 | V | VDD = 1.8V; max printed as VDD | 7 | ||
| Input Low Voltage, 1G, 1.8V | VIL | 0.6 | V | VDD = 1.8V | 7 | ||
| Output High Voltage, 1.8V | VOH | 1.4 | V | IOH = -5mA | 7 | ||
| Output Low Voltage, 1.8V | VOL | 0.4 | V | IOL = 5mA | 7 | ||
| Operating Supply Current, 5PB1108, 1.8V | IDD | 20 | 23 | mA | 100MHz, no load, 25°C | 7 | |
| Input High Leakage, 1.8V | IIH | 5 | µA | VIN = VDD | 7 | ||
| Input Low Leakage, 1.8V | IIL | 5 | µA | VIN = 0V | 7 | ||
| Operating Voltage, 2.5V | VDD | 2.375 | 2.5 | 2.625 | V | VDD = 2.5V ±5%, Industrial | 9 |
| Input High Voltage, 1G, 2.5V | VIH | 1.8 | V | VDD = 2.5V; max printed as VDD | 9 | ||
| Input Low Voltage, 1G, 2.5V | VIL | 0.7 | V | VDD = 2.5V | 9 | ||
| Output High Voltage, 2.5V | VOH | 1.9 | V | IOH = -8mA | 9 | ||
| Output Low Voltage, 2.5V | VOL | 0.5 | V | IOL = 8mA | 9 | ||
| Operating Supply Current, 5PB1108, 2.5V | IDD | 27 | 31 | mA | 100MHz, no load, 25°C | 9 | |
| Input High Leakage, 2.5V | IIH | 5 | µA | VIN = VDD | 9 | ||
| Input Low Leakage, 2.5V | IIL | 5 | µA | VIN = 0V | 9 | ||
| Operating Voltage, 3.3V | VDD | 3.135 | 3.3 | 3.465 | V | VDD = 3.3V ±5%, Industrial | 11 |
| Input High Voltage, 1G, 3.3V | VIH | 2 | V | VDD = 3.3V; max printed as VDD | 11 | ||
| Input Low Voltage, 1G, 3.3V | VIL | 0.8 | V | VDD = 3.3V | 11 | ||
| Output High Voltage, 3.3V | VOH | 2.4 | V | IOH = -12mA | 11 | ||
| Output Low Voltage, 3.3V | VOL | 0.7 | V | IOL = 12mA | 11 | ||
| Operating Supply Current, 5PB1108, 3.3V | IDD | 35 | 38 | mA | 100MHz, no load, 25°C | 11 | |
| Input High Leakage, 3.3V | IIH | 5 | µA | VIN = VDD | 11 | ||
| Input Low Leakage, 3.3V | IIL | 5 | µA | VIN = 0V | 11 | ||
| Input Frequency | 0 | 200 | MHz | Industrial and Extended | 13 | ||
| Output Rise Time (2pF load), 1.8V | tOR | 0.5 | 0.75 | ns | 0.36V to 1.44V, CL = 2pF | 13 | |
| Output Rise Time (5pF load), 1.8V | tOR | 0.8 | 1 | ns | 0.36V to 1.44V, CL = 5pF | 13 | |
| Start-up Time, 1.8V | tSTART-UP | 3 | ms | Part start-up time for valid outputs after VDD ramp-up | 13 | ||
| Propagation Delay, 1.8V | tPD | 1.5 | 2.5 | ns | With rail-to-rail input clock | 13 | |
| Buffer Additive Phase Jitter, RMS, 1.8V | 0.05 | ps | 156.25MHz, Integration Range: 12kHz-20MHz | 13 | |||
| Output to Output Skew, 5PB1108/10, 1.8V | 45 | 65 | ps | Rising edges at VDD/2 | 13 | ||
| Device to Device Skew, 1.8V | 200 | ps | Rising edges at VDD/2 | 13 | |||
| Output Enable Time | tEN | 3 | cycles | CL < 5pF | 13 | ||
| Output Disable Time | tDIS | 3 | cycles | CL < 5pF | 13 | ||
| Output Rise Time (2pF load), 2.5V | tOR | 0.4 | 0.7 | ns | 0.5V to 2.0V, CL = 2pF | 15 | |
| Output Rise Time (5pF load), 2.5V | tOR | 0.75 | 1 | ns | 0.5V to 2.0V, CL = 5pF | 15 | |
| Propagation Delay, 5PB1106/08, 2.5V | tPD | 2 | 3.3 | ns | With rail-to-rail input clock | 15 | |
| Buffer Additive Phase Jitter, RMS, 2.5V | 0.05 | ps | 156.25MHz, Integration Range: 12kHz-20MHz | 15 | |||
| Output to Output Skew, 5PB1108/10, 2.5V | 45 | 65 | ps | Rising edges at VDD/2 | 15 | ||
| Output Rise Time (2pF load), 3.3V | tOR | 0.45 | 0.6 | ns | 0.66V to 2.64V, CL = 2pF | 17 | |
| Output Rise Time (5pF load), 3.3V | tOR | 0.7 | 1 | ns | 0.66V to 2.64V, CL = 5pF | 17 | |
| Propagation Delay, 5PB1106/08, 3.3V | tPD | 1.7 | 2.7 | ns | With rail-to-rail input clock | 17 | |
| Buffer Additive Phase Jitter, RMS, 3.3V | 0.05 | ps | 156.25MHz, Integration Range: 12kHz-20MHz | 17 | |||
| Output to Output Skew, 5PB1108/10, 3.3V | 45 | 65 | ps | Rising edges at VDD/2 | 17 | ||
| Nominal Output Impedance | ZO | 50 | Ω | 7 | |||
| Input Capacitance | CIN | 5 | pF | CLKIN, 1G pin | 7 | ||
| Duty Cycle | tDC | 50 | % | 13 |
CAD (KiCad official)
- Symbol:
5PB1108PGGI - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
5pb1108pggi-etched.step/5pb1108pggi-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);5pb1108pggi.step/5pb1108pggi.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (41 pp, sha256
4080ec0ffb504d38, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).