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SQ1563AEH-T1_GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SOT-363-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSQ1563AEH-T1_GE3
Vishay Intertech · MOSFETs · SOT-363-6
SQ1563AEH-T1_GE3 from Vishay Intertech, in a SOT-363-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of the N-channel MOSFET (Q1), rated 20 V VDS and 0.85 A continuous drain current. |
| 2 | G1 | input | Gate of the N-channel MOSFET (Q1), with gate-source voltage limited to ±8 V. |
| 3 | D2 | passive | Drain of the P-channel MOSFET (Q2), rated -20 V VDS and -0.85 A continuous drain current. |
| 4 | S2 | passive | Source of the P-channel MOSFET (Q2), rated -20 V VDS and -0.85 A continuous source current. |
| 5 | G2 | input | Gate of the P-channel MOSFET (Q2), with gate-source voltage limited to ±8 V. |
| 6 | D1 | passive | Drain of the N-channel MOSFET (Q1), rated 20 V VDS and 0.85 A continuous drain current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SOT-363-6 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage N-Ch | VDS | 20 | V | TC = 25 °C | 1 | ||
| Drain-source voltage P-Ch | VDS | -20 | V | TC = 25 °C | 1 | ||
| Gate-source voltage | VGS | -8 | 8 | V | TC = 25 °C | 1 | |
| Continuous drain current N-Ch | ID | 0.85 | A | TC = 25 °C | 1 | ||
| Continuous drain current P-Ch | ID | -0.85 | A | TC = 25 °C | 1 | ||
| Continuous drain current P-Ch | ID | -0.79 | A | TC = 125 °C | 1 | ||
| Continuous source current N-Ch | IS | 0.85 | A | diode conduction | 1 | ||
| Continuous source current P-Ch | IS | -0.85 | A | diode conduction | 1 | ||
| Pulsed drain current N-Ch | IDM | 3.3 | A | Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 % | 1 | ||
| Pulsed drain current P-Ch | IDM | -3.3 | A | Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 % | 1 | ||
| Single pulse avalanche current N-Ch | IAS | 3.5 | A | L = 0.1 mH | 1 | ||
| Single pulse avalanche current P-Ch | IAS | -1.4 | A | L = 0.1 mH | 1 | ||
| Single pulse avalanche energy N-Ch | EAS | 0.6 | mJ | L = 0.1 mH | 1 | ||
| Single pulse avalanche energy P-Ch | EAS | 0.1 | mJ | L = 0.1 mH | 1 | ||
| Maximum power dissipation | PD | 1.5 | W | TC = 25 °C | 1 | ||
| Maximum power dissipation | PD | 0.5 | W | TC = 125 °C | 1 | ||
| Operating junction and storage temperature range | TJ, Tstg | -55 | 175 | °C | 1 | ||
| Junction-to-ambient thermal resistance | RthJA | 220 | °C/W | PCB mount, 1" square PCB (FR4) | 1 | ||
| Junction-to-foot (drain) thermal resistance | RthJF | 100 | °C/W | 1 | |||
| Drain-source breakdown voltage N-Ch | VDS | 20 | V | VGS = 0 V, ID = 250 μA | 2 | ||
| Drain-source breakdown voltage P-Ch | VDS | -20 | V | VGS = 0 V, ID = -250 μA | 2 | ||
| Gate-source threshold voltage N-Ch | VGS(th) | 0.45 | 0.6 | 1.5 | V | VDS = VGS, ID = 250 μA | 2 |
| Gate-source threshold voltage P-Ch | VGS(th) | -0.45 | -0.6 | -1.5 | V | VDS = VGS, ID = -250 μA | 2 |
| Gate-source leakage N-Ch | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 8 V | 2 | |
| Gate-source leakage P-Ch | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 8 V | 2 | |
| Zero gate voltage drain current N-Ch | IDSS | 1 | μA | VGS = 0 V, VDS = 20 V | 2 | ||
| Zero gate voltage drain current P-Ch | IDSS | -1 | μA | VGS = 0 V, VDS = -20 V | 2 | ||
| Zero gate voltage drain current N-Ch | IDSS | 50 | μA | VGS = 0 V, VDS = 20 V, TJ = 125 °C | 2 | ||
| Zero gate voltage drain current P-Ch | IDSS | -50 | μA | VGS = 0 V, VDS = -20 V, TJ = 125 °C | 2 | ||
| Zero gate voltage drain current N-Ch | IDSS | 150 | μA | VGS = 0 V, VDS = 20 V, TJ = 175 °C | 2 | ||
| Zero gate voltage drain current P-Ch | IDSS | -150 | μA | VGS = 0 V, VDS = -20 V, TJ = 175 °C | 2 | ||
| On-state drain current N-Ch | ID(on) | 2 | A | VGS = 4.5 V, VDS ≥ 5 V | 2 | ||
| On-state drain current P-Ch | ID(on) | -2 | A | VGS = -4.5 V, VDS ≤ -5 V | 2 | ||
| Drain-source on-state resistance N-Ch | RDS(on) | 0.15 | 0.28 | Ω | VGS = 4.5 V, ID = 0.85 A | 2 | |
| Drain-source on-state resistance P-Ch | RDS(on) | 0.5 | 0.575 | Ω | VGS = -4.5 V, ID = -0.80 A | 2 | |
| Drain-source on-state resistance N-Ch | RDS(on) | 0.18 | 0.36 | Ω | VGS = 2.5 V, ID = 0.85 A | 2 | |
| Drain-source on-state resistance P-Ch | RDS(on) | 1.05 | 1.3 | Ω | VGS = -2.5 V, ID = -0.60 A | 2 | |
| Drain-source on-state resistance N-Ch | RDS(on) | 0.21 | 0.45 | Ω | VGS = 1.8 V, ID = 0.85 A | 2 | |
| Drain-source on-state resistance P-Ch | RDS(on) | 1.2 | 1.5 | Ω | VGS = -1.8 V, ID = -0.20 A | 2 | |
| Input capacitance N-Ch | Ciss | 67 | 89 | pF | VGS = 0 V, VDS = 10 V, f = 1 MHz | 2 | |
| Input capacitance P-Ch | Ciss | 63 | 84 | pF | VGS = 0 V, VDS = -10 V, f = 1 MHz | 2 | |
| Output capacitance N-Ch | Coss | 22 | 29 | pF | VGS = 0 V, VDS = 10 V, f = 1 MHz | 2 | |
| Output capacitance P-Ch | Coss | 26 | 34 | pF | VGS = 0 V, VDS = -10 V, f = 1 MHz | 2 | |
| Reverse transfer capacitance N-Ch | Crss | 10 | 13 | pF | VGS = 0 V, VDS = 10 V, f = 1 MHz | 2 | |
| Reverse transfer capacitance P-Ch | Crss | 10 | 13 | pF | VGS = 0 V, VDS = -10 V, f = 1 MHz | 2 | |
| Gate resistance N-Ch | Rg | 3.8 | 11.6 | Ω | f = 1 MHz | 2 | |
| Gate resistance P-Ch | Rg | 3.1 | 9.5 | Ω | f = 1 MHz | 2 | |
| Total gate charge N-Ch | Qg | 0.93 | 1.25 | nC | VGS = 4.5V, VDS = 10 V, ID = 0.85 A | 2 | |
| Total gate charge P-Ch | Qg | 1 | 1.33 | nC | VGS = -4.5 V, VDS = -10 V, ID = -0.85 A | 2 | |
| Turn-on delay time N-Ch | td(on) | 3 | 6 | ns | VDD = 10 V, RL = 20 Ω, ID ≅ 0.5 A, VGEN = 4.5 V, Rg = 1 Ω | 3 | |
| Turn-on delay time P-Ch | td(on) | 2 | 4 | ns | VDD = -10 V, RL = 20 Ω, ID ≅ -0.5 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Rise time N-Ch | tr | 21 | 27 | ns | VDD = 10 V, RL = 20 Ω, ID ≅ 0.5 A, VGEN = 4.5 V, Rg = 1 Ω | 3 | |
| Rise time P-Ch | tr | 22 | 28 | ns | VDD = -10 V, RL = 20 Ω, ID ≅ -0.5 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Turn-off delay time N-Ch | td(off) | 20 | 25 | ns | VDD = 10 V, RL = 20 Ω, ID ≅ 0.5 A, VGEN = 4.5 V, Rg = 1 Ω | 3 | |
| Turn-off delay time P-Ch | td(off) | 28 | 35 | ns | VDD = -10 V, RL = 20 Ω, ID ≅ -0.5 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Fall time N-Ch | tf | 17 | 24 | ns | VDD = 10 V, RL = 20 Ω, ID ≅ 0.5 A, VGEN = 4.5 V, Rg = 1 Ω | 3 | |
| Fall time P-Ch | tf | 20 | 25 | ns | VDD = 10 V, RL = 20 Ω, ID ≅ -0.5 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Pulsed source current N-Ch | ISM | 3.3 | A | 3 | |||
| Pulsed source current P-Ch | ISM | -3.3 | A | 3 | |||
| Forward voltage N-Ch | VSD | 0.9 | 1.2 | V | IS = 0.85 A | 3 | |
| Forward voltage P-Ch | VSD | -0.9 | -1.2 | V | IS = -0.85 A | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | Dual-Channel LITTLE FOOT® 6-Pin SC-70 MOSFET Copper Leadframe Version | 12 |
CAD (KiCad official)
- Symbol:
SQ1563AEH-T1_GE3 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363-6 (KiCad packages3D, STEP)
- 3D model files:
sq1563aeh-t1-ge3-etched.step/sq1563aeh-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sq1563aeh-t1-ge3.step/sq1563aeh-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (15 pp, sha256
9a65a3ca4fe51bfb, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).