component
CY8C20236A-24LKXIT
Public Made by Adomby adom
Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownCY8C20236A-24LKXIT
Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-16(3x3)
CY8C20236A-24LKXIT from Cypress Semicon, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P2[5] | bidirectional | Digital I/O with analog input; crystal output (XOut). |
| 2 | P2[3] | bidirectional | Digital I/O with analog input; crystal input (XIn). |
| 3 | P1[7] | bidirectional | 5 mA high-drive regulated-output digital I/O with analog input; I2C SCL, SPI SS. |
| 4 | P1[5] | bidirectional | 5 mA high-drive regulated-output digital I/O with analog input; I2C SDA, SPI MISO. |
| 5 | P1[3] | bidirectional | 5 mA high-drive regulated-output digital I/O with analog input; SPI CLK. |
| 6 | P1[1] | bidirectional | 5 mA high-drive regulated-output digital I/O with analog input; ISSP CLK, I2C SCL, SPI MOSI; may disturb the I2C bus during power-up or reset. |
| 7 | VSS | power_in | Ground connection; all VSS pins should be brought out to one common GND plane. |
| 8 | P1[0] | bidirectional | 5 mA high-drive regulated-output digital I/O with analog input; ISSP DATA, I2C SDA, alternate SPI CLK; may disturb the I2C bus during power-up or reset. |
| 9 | P1[2] | bidirectional | 5 mA high-drive regulated-output digital I/O with analog input. |
| 10 | P1[4] | bidirectional | 5 mA high-drive regulated-output digital I/O with analog input; optional external clock (EXTCLK). |
| 11 | XRES | input | Active high external reset with internal pull-down. |
| 12 | P0[4] | bidirectional | 5 mA high-drive digital I/O with analog input. |
| 13 | VDD | power_in | Supply voltage. |
| 14 | P0[7] | bidirectional | 5 mA high-drive digital I/O with analog input. |
| 15 | P0[3] | bidirectional | 5 mA high-drive digital I/O with analog input; integrating input. |
| 16 | P0[1] | bidirectional | 5 mA high-drive digital I/O with analog input; integrating input. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | QFN-16(3x3) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TSTG | -55 | 25 | 125 | °C | Higher storage temperatures reduce data retention time | 20 |
| Supply voltage relative to VSS | VDD | -0.5 | 6 | V | 20 | ||
| Maximum current into any port pin | IMIO | -25 | 50 | mA | 20 | ||
| Electrostatic discharge voltage | ESD | 2000 | V | Human body model ESD | 20 | ||
| Latch-up current | LU | 200 | mA | In accordance with JESD78 standard | 20 | ||
| Ambient temperature | TA | -40 | 85 | °C | 20 | ||
| Commercial temperature range | TC | 0 | 70 | °C | 20 | ||
| Operational die temperature | TJ | -40 | 100 | °C | Temperature rise from ambient to junction is package specific | 20 | |
| Supply voltage | VDD | 1.71 | 5.5 | V | No USB activity | 21 | |
| Supply current, IMO = 24 MHz | IDD24 | 2.88 | 4 | mA | TA = 25 °C, CPU = 24 MHz, CapSense running at 12 MHz, no I/O sourcing current | 21 | |
| Supply current, IMO = 12 MHz | IDD12 | 1.71 | 2.6 | mA | TA = 25 °C, CPU = 12 MHz, CapSense running at 12 MHz, no I/O sourcing current | 21 | |
| Supply current, IMO = 6 MHz | IDD6 | 1.16 | 1.8 | mA | TA = 25 °C, CPU = 6 MHz, CapSense running at 6 MHz, no I/O sourcing current | 21 | |
| Deep sleep current | ISB0 | 0.1 | 1.05 | µA | TA = 25 °C, I/O regulator turned off | 21 | |
| Standby current with POR, LVD and sleep timer | ISB1 | 1.07 | 1.5 | µA | TA = 25 °C, I/O regulator turned off | 21 | |
| Standby current with I2C enabled | ISBI2C | 1.64 | µA | VDD = 3.3 V, TA = 25 °C and CPU = 24 MHz | 21 | ||
| Pull-up resistor (2.4-3.0 V) | RPU | 4 | 5.6 | 8 | kΩ | 23 | |
| High output voltage, Port 1 LDO 1.8 V out | VOH5A | 1.5 | 1.8 | 2.1 | V | IOH < 10 µA, VDD > 2.4 V, max 20 mA source current in all I/Os | 23 |
| High output voltage, Port 1 LDO 1.8 V out | VOH6A | 1.2 | V | IOH = 1 mA, VDD > 2.4 V, max 20 mA source current in all I/Os | 23 | ||
| Low output voltage (2.4-3.0 V) | VOL | 0.75 | V | IOL = 10 mA | 23 | ||
| Input low voltage (2.4-3.0 V) | VIL | 0.72 | V | 23 | |||
| Input high voltage (2.4-3.0 V) | VIH | 1.4 | V | 23 | |||
| Input hysteresis voltage (2.4-3.0 V) | VH | 80 | mV | 23 | |||
| Input leakage (2.4-3.0 V) | IIL | 1 | 1000 | nA | 23 | ||
| Capacitive load on pins (2.4-3.0 V) | CPIN | 0.5 | 1.7 | 7 | pF | Package and pin dependent, Temp = 25 °C | 23 |
| Input low voltage with low threshold enable | VILLVT2.5 | 0.7 | V | Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input | 23 | ||
| Input high voltage with low threshold enable | VIHLVT2.5 | 1.2 | V | Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input | 23 | ||
| Pull-up resistor (1.71-2.4 V) | RPU | 4 | 5.6 | 8 | kΩ | 23 | |
| Low output voltage (1.71-2.4 V) | VOL | 0.4 | V | IOL = 5 mA | 23 | ||
| Input hysteresis voltage (1.71-2.4 V) | VH | 80 | mV | 24 | |||
| Input leakage (1.71-2.4 V) | IIL | 1 | 1000 | nA | 24 | ||
| Capacitive load on pins (1.71-2.4 V) | CPIN | 0.5 | 1.7 | 7 | pF | Package and pin dependent, temp = 25 °C | 24 |
| Switch resistance to common analog bus | RSW | 800 | Ω | 24 | |||
| Resistance of initialization switch to VSS | RGND | 800 | Ω | 24 | |||
| LPC common mode | VLPC | 0 | 1.8 | V | Maximum voltage limited to VDD | 24 | |
| LPC supply current | ILPC | 10 | 40 | µA | 24 | ||
| LPC voltage offset | VOSLPC | 3 | 30 | mV | 24 | ||
| Comparator response time | tCOMP | 70 | 100 | ns | 50 mV overdrive | 25 | |
| Comparator offset | Offset | 2.5 | 30 | mV | Valid from 0.2 V to VDD, 0.2 V | 25 | |
| Comparator average DC current | Current | 20 | 80 | µA | 50 mV overdrive | 25 | |
| Comparator input range | 0 | 1.5 | V | 25 | |||
| ADC input capacitance | CIIN | 5 | pF | 25 | |||
| ADC reference voltage | VREFADC | 1.14 | 1.26 | V | 25 | ||
| ADC data clock | FCLK | 2.25 | 6 | MHz | Source is chip's internal main oscillator | 25 | |
| ADC resolution | RES | 8 | 10 | bits | Can be set to 8-, 9-, or 10-bit | 25 | |
| ADC differential nonlinearity | DNL | -1 | 2 | LSB | 25 | ||
| ADC integral nonlinearity | INL | -2 | 2 | LSB | 25 | ||
| ADC offset error, 8-bit | EOFFSET | 0 | 3.2 | 19.2 | LSB | 8-bit resolution | 25 |
| ADC offset error, 10-bit | EOFFSET | 0 | 12.8 | 76.8 | LSB | 10-bit resolution | 25 |
| ADC gain error | EGAIN | -5 | 5 | %FSR | For any resolution | 25 | |
| ADC operating current | IADC | 2.1 | 2.6 | mA | 25 | ||
| POR 1.66 V selected | VPOR0 | 1.61 | 1.66 | 1.71 | V | VDD must be greater than or equal to 1.71 V during startup, reset from XRES, or watchdog | 26 |
| POR 2.36 V selected | VPOR1 | 2.36 | 2.41 | V | 26 | ||
| POR 2.60 V selected | VPOR2 | 2.6 | 2.66 | V | 26 | ||
| POR 2.82 V selected | VPOR3 | 2.82 | 2.95 | V | 26 | ||
| LVD 2.45 V selected | VLVD0 | 2.4 | 2.45 | 2.51 | V | 26 | |
| LVD 2.71 V selected | VLVD1 | 2.64 | 2.71 | 2.78 | V | 26 | |
| LVD 2.92 V selected | VLVD2 | 2.85 | 2.92 | 2.99 | V | 26 | |
| LVD 3.02 V selected | VLVD3 | 2.95 | 3.02 | 3.09 | V | 26 | |
| LVD 3.13 V selected | VLVD4 | 3.06 | 3.13 | 3.2 | V | 26 | |
| LVD 1.90 V selected | VLVD5 | 1.84 | 1.9 | 2.32 | V | 26 | |
| LVD 1.80 V selected | VLVD6 | 1.75 | 1.8 | 1.84 | V | 26 | |
| LVD 4.73 V selected | VLVD7 | 4.62 | 4.73 | 4.83 | V | 26 | |
| Supply voltage for flash write operations | VDDIWRITE | 1.71 | 5.25 | V | 26 | ||
| Supply current during programming or verify | IDDP | 5 | 25 | mA | 26 | ||
| Flash write endurance | FlashENPB | 50000 | cycles | Erase/write cycles per block | 26 | ||
| Flash data retention | FlashDR | 20 | Years | Following maximum Flash write cycles; ambient temperature of 55 °C | 26 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | The emulator consists of a base unit that connects to the PC | 8 |
CAD (KiCad official)
- Symbol:
CY8C20236A-24LKXIT - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
cy8c20236a-24lkxit-etched.step/cy8c20236a-24lkxit-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c20236a-24lkxit.step/cy8c20236a-24lkxit.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (53 pp, sha256
202cb04641c7ff9b, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).