2309-1DCGI from RENESAS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	REF	input	Input reference clock, 5 Volt tolerant input, with threshold voltage of VDD/2.
2	CLKA1	output	Output clock for bank A, with weak pull down.
3	CLKA2	output	Output clock for bank A, with weak pull down.
4	VDD	power_in	3.3V supply (3 to 3.6V operating range).
5	GND	power_in	Ground.
6	CLKB1	output	Output clock for bank B, with weak pull down.
7	CLKB2	output	Output clock for bank B, with weak pull down.
8	S2	input	Select input bit 2, with weak pull up; with S1 sets bank output states and PLL shutdown per function table.
9	S1	input	Select input bit 1, with weak pull up; with S2 sets bank output states and PLL shutdown per function table.
10	CLKB3	output	Output clock for bank B, with weak pull down.
11	CLKB4	output	Output clock for bank B, with weak pull down.
12	GND	power_in	Ground.
13	VDD	power_in	3.3V supply (3 to 3.6V operating range).
14	CLKA3	output	Output clock for bank A, with weak pull down.
15	CLKA4	output	Output clock for bank A, with weak pull down.
16	CLKOUT	output	Output clock with internal PLL feedback on this pin, with weak pull down; always driven in all S2/S1 modes.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-16
Category	Clock/Timing
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage Range	VDD	-0.5		4.6	V		2
Input Voltage Range (REF)	VI	-0.5		5.5	V	REF pin	2
Input Voltage Range (except REF)	VI	-0.5			V	max printed as VDD+0.5	2
Input Clamp Current	IIK			-50	mA	VI < 0	2
Continuous Output Current	IO	-50		50	mA	VO = 0 to VDD	2
VDD or GND Continuous Current		-100		100	mA		2
Maximum Power Dissipation				0.7	W	TA = 55°C, in still air	2
Storage Temperature Range	TSTG	-65		150	°C		2
Supply Voltage	VDD	3		3.6	V	Industrial	4
Operating Temperature (Ambient)	TA	-40		85	°C	Industrial	4
Load Capacitance	CL			30	pF	< 100MHz	4
Load Capacitance	CL			10	pF	100MHz - 133MHz	4
Input Capacitance	CIN			7	pF		4
Input LOW Voltage Level	VIL			0.8	V		4
Input HIGH Voltage Level	VIH	2			V		4
Input LOW Current	IIL			50	µA	VIN = 0V	4
Input HIGH Current	IIH			100	µA	VIN = VDD	4
Output LOW Voltage	VOL			0.4	V	Standard Drive IOL = 8mA	4
Output HIGH Voltage	VOH	2.4			V	Standard Drive IOH = -8mA	4
Power Down Current	IDD_PD			25	µA	REF = 0MHz (S2 = S1 = H)	4
Supply Current	IDD			35	mA	Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND	4
Output Frequency	t1	10		133	MHz	10pF Load	5
Output Frequency	t1	10		100	MHz	30pF Load	5
Duty Cycle = t2 ÷ t1		40	50	60	%	Measured at 1.4V, FOUT = 66.66MHz	5
Rise Time	t3			2.5	ns	Measured between 0.8V and 2V	5
Fall Time	t4			2.5	ns	Measured between 0.8V and 2V	5
Output to Output Skew	t5			250	ps	All outputs equally loaded	5
Delay, REF Rising Edge to CLKOUT Rising Edge	t6A	-350	0	350	ps	Measured at VDD/2	5
Delay, REF Rising Edge to CLKOUT Rising Edge (PLL bypass)	t6B	1	5	8.7	ns	Measured at VDD/2 in PLL bypass mode (IDT2309 only)	5
Device-to-Device Skew	t7		0	700	ps	Measured at VDD/2 on the CLKOUT pins of devices	5
Cycle-to-Cycle Jitter	tJ			200	ps	Measured at 66.66MHz, loaded outputs	5
PLL Lock Time	tLOCK			1	ms	Stable power supply, valid clock presented on REF pin	5

CAD (KiCad official)

Symbol: 2309-1DCGI
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: 2309-1dcgi-etched.step / 2309-1dcgi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2309-1dcgi.step / 2309-1dcgi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (11 pp, sha256 261bb6553c4e8923, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

2309-1DCGI

Verified 2309-1DCGI

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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