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CD74HC138QM96Q1

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Texas Instruments Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hc138qm96q1factory-2.0.0extractor-text

Verified CD74HC138QM96Q1

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HC138QM96Q1 · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 9-page datasheet
  • ✓distributor: lcsc C2674684, digikey 296-31565-2-ND, mouser 595-CD74HC138QM96Q1
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9fryb5ek/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hc138qm96q1.kicad_sym✓ cd74hc138qm96q1.kicad_mod✓ cd74hc138qm96q1.step
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Contents

README

markdown

CD74HC138QM96Q1

Texas Instruments · Signal Switches, Multiplexers, Decoders · SOIC-16

CD74HC138QM96Q1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Binary select input A0 (LSB) of the 3-to-8 decoder; logic levels follow the VIH/VIL limits over the 2 V to 6 V VCC range.
2 A1 input Binary select input A1 of the 3-to-8 decoder; logic levels follow the VIH/VIL limits over the 2 V to 6 V VCC range.
3 A2 input Binary select input A2 (MSB) of the 3-to-8 decoder; logic levels follow the VIH/VIL limits over the 2 V to 6 V VCC range.
4 E1 input Active-low enable input that must be low, together with E2 low and E3 high, for the outputs to be selected.
5 E2 input Active-low enable input that must be low, together with E1 low and E3 high, for the outputs to be selected.
6 E3 input Active-high enable input that must be high, together with E1 and E2 low, for the outputs to be selected.
7 Y7 output Active-low decoder output that goes low when address 7 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
8 GND power_in Ground reference; all voltages are referenced to GND.
9 Y6 output Active-low decoder output that goes low when address 6 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
10 Y5 output Active-low decoder output that goes low when address 5 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
11 Y4 output Active-low decoder output that goes low when address 4 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
12 Y3 output Active-low decoder output that goes low when address 3 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
13 Y2 output Active-low decoder output that goes low when address 2 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
14 Y1 output Active-low decoder output that goes low when address 1 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
15 Y0 output Active-low decoder output that goes low when address 0 is selected with the device enabled; standard outputs drive 10 LSTTL loads.
16 VCC power_in Supply pin; operating supply range is 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V All voltages referenced to GND 3
Input clamp current IIK -20 20 mA VI < −0.5 V or VI > VCC + 0.5 V 3
Output clamp current IOK -20 20 mA VO < −0.5 V or VO > VCC + 0.5 V 3
Source or sink current per output pin IO -25 25 mA VO > −0.5 V or VO < VCC + 0.5 V 3
Continuous current through VCC or GND -50 50 mA 3
Storage temperature range Tstg -65 150 °C 3
Supply voltage VCC 2 6 V 3
High-level input voltage VIH 1.5 V VCC = 2 V 3
High-level input voltage VIH 3.15 V VCC = 4.5 V 3
High-level input voltage VIH 4.2 V VCC = 6 V 3
Low-level input voltage VIL 0.5 V VCC = 2 V 3
Low-level input voltage VIL 1.35 V VCC = 4.5 V 3
Low-level input voltage VIL 1.8 V VCC = 6 V 3
Input transition (rise and fall) time tt 1000 ns VCC = 2 V 3
Input transition (rise and fall) time tt 500 ns VCC = 4.5 V 3
Input transition (rise and fall) time tt 400 ns VCC = 6 V 3
Operating free-air temperature TA -40 125 °C 3
High-level output voltage, CMOS loads VOH 1.9 V TA = 25°C; VI = VIH or VIL; IO = −0.02 mA; VCC = 2 V 4
High-level output voltage, CMOS loads VOH 4.4 V TA = 25°C; VI = VIH or VIL; IO = −0.02 mA; VCC = 4.5 V 4
High-level output voltage, CMOS loads VOH 5.9 V TA = 25°C; VI = VIH or VIL; IO = −0.02 mA; VCC = 6 V 4
High-level output voltage, TTL loads VOH 3.98 V TA = 25°C; VI = VIH or VIL; IO = −4 mA; VCC = 4.5 V 4
High-level output voltage, TTL loads VOH 3.7 V TA = −40°C to 125°C; VI = VIH or VIL; IO = −4 mA; VCC = 4.5 V 4
High-level output voltage, TTL loads VOH 5.48 V TA = 25°C; VI = VIH or VIL; IO = −5.2 mA; VCC = 6 V 4
High-level output voltage, TTL loads VOH 5.2 V TA = −40°C to 125°C; VI = VIH or VIL; IO = −5.2 mA; VCC = 6 V 4
Low-level output voltage, CMOS loads VOL 0.1 V TA = 25°C; VI = VIH or VIL; IO = 0.02 mA; VCC = 2 V 4
Low-level output voltage, TTL loads VOL 0.26 V TA = 25°C; VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V 4
Low-level output voltage, TTL loads VOL 0.4 V TA = −40°C to 125°C; VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V 4
Input leakage current II -1 1 µA VI = VCC or GND; VCC = 6 V 4
Quiescent supply current ICC 8 160 µA VI = VCC or GND; IO = 0; VCC = 6 V 4
Input capacitance CIN 10 pF 4
Propagation delay A to Y tpd 13 ns CL = 15 pF; VCC = 5 V; TA = 25°C 4
Propagation delay A to Y, 25°C tpd 150 ns CL = 50 pF; VCC = 2 V; TA = 25°C 4
Propagation delay A to Y, 25°C tpd 30 ns CL = 50 pF; VCC = 4.5 V; TA = 25°C 4
Propagation delay A to Y, 25°C tpd 26 ns CL = 50 pF; VCC = 6 V; TA = 25°C 4
Propagation delay A to Y, 125°C tpd 225 ns CL = 50 pF; VCC = 2 V; TA = −40°C to 125°C 4
Propagation delay A to Y, 125°C tpd 45 ns CL = 50 pF; VCC = 4.5 V; TA = −40°C to 125°C 4
Propagation delay A to Y, 125°C tpd 38 ns CL = 50 pF; VCC = 6 V; TA = −40°C to 125°C 4
Propagation delay E to Y, 25°C tpd 150 ns CL = 50 pF; VCC = 2 V; TA = 25°C 4
Propagation delay E to Y, 25°C tpd 30 ns CL = 50 pF; VCC = 4.5 V; TA = 25°C 4
Propagation delay E to Y, 25°C tpd 26 ns CL = 50 pF; VCC = 6 V; TA = 25°C 4
Propagation delay E to Y, 125°C tpd 265 ns CL = 50 pF; VCC = 2 V; TA = −40°C to 125°C 4
Propagation delay E to Y, 125°C tpd 53 ns CL = 50 pF; VCC = 4.5 V; TA = −40°C to 125°C 4
Propagation delay E to Y, 125°C tpd 45 ns CL = 50 pF; VCC = 6 V; TA = −40°C to 125°C 4
Output transition time tt 75 ns CL = 50 pF; VCC = 2 V; TA = 25°C 4
Output transition time tt 15 ns CL = 50 pF; VCC = 4.5 V; TA = 25°C 4
Output transition time tt 13 ns CL = 50 pF; VCC = 6 V; TA = 25°C 4
Output transition time, 125°C tt 110 ns CL = 50 pF; VCC = 2 V; TA = −40°C to 125°C 4
Output transition time, 125°C tt 22 ns CL = 50 pF; VCC = 4.5 V; TA = −40°C to 125°C 4
Output transition time, 125°C tt 19 ns CL = 50 pF; VCC = 6 V; TA = −40°C to 125°C 4
Power dissipation capacitance Cpd 67 pF VCC = 5 V; TA = 25°C; per gate 4
Package thermal impedance θJA 73 °C/W Calculated per JESD 51-7 3

CAD (KiCad official)

  • Symbol: CD74HC138QM96Q1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc138qm96q1-etched.step / cd74hc138qm96q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc138qm96q1.step / cd74hc138qm96q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (9 pp, sha256 9c2e8a52e318fe73, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF