Symbol & Footprint

Schematic Symbol

Open full view ↗

PCB Footprint

Open full view ↗
Contents

README

markdown

SN74HC193DR

Texas Instruments · Counters / Dividers · SOIC-16

SN74HC193DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Parallel data input B (bit 1). Preset value loaded into flip-flop QB when LOAD is low. High-level input threshold 3.15 V at VCC=4.5 V; input current 1 uA max.
2 QB output Counter data output bit 1 (QB). CMOS push-pull output; +/-4 mA drive at 5 V; can drive up to 10 LSTTL loads.
3 QA output Counter data output bit 0 (QA, LSB). CMOS push-pull output; +/-4 mA drive at 5 V.
4 DOWN input Count-down clock input. Counter decrements on a low-to-high transition of DOWN while UP is held high. Rise/fall time <= 500 ns at VCC=4.5 V.
5 UP input Count-up clock input. Counter increments on a low-to-high transition of UP while DOWN is held high.
6 QC output Counter data output bit 2 (QC). CMOS push-pull output; +/-4 mA drive at 5 V.
7 QD output Counter data output bit 3 (QD, MSB). CMOS push-pull output; +/-4 mA drive at 5 V.
8 GND power_in Ground reference (0 V). Continuous current through VCC or GND +/-50 mA max.
9 D input Parallel data input D (bit 3, MSB). Preset value loaded into flip-flop QD when LOAD is low.
10 C input Parallel data input C (bit 2). Preset value loaded into flip-flop QC when LOAD is low.
11 LOAD input Asynchronous parallel-load enable, active-low. Driving LOAD low forces the counter outputs to match the A/B/C/D data inputs, independent of the count clocks.
12 CO output Carry output, active-low. Produces a low-level pulse when the count reaches maximum (15) and UP is low. Feed to the UP input of the next stage to cascade counters.
13 BO output Borrow output, active-low. Produces a low-level pulse when the count is zero (all outputs low) and DOWN is low. Feed to the DOWN input of the next stage to cascade counters.
14 CLR input Asynchronous clear, active-high. When high, forces all Q outputs to logic low regardless of LOAD, data, or count inputs.
15 A input Parallel data input A (bit 0, LSB). Preset value loaded into flip-flop QA when LOAD is low.
16 VCC power_in Positive supply voltage. Operating range 2 V to 6 V (5 V nominal); absolute max 7 V. Quiescent current 80 uA max.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SN74HC193DRD
  • SN74HC193DR
  • SN74HC193DRDT
  • SN74HC193DRN
  • SN74HC193DRNSR
  • SN74HC193DRPW
  • SN74HC193DRPWR
  • SN74HC193DRPWT
  • SN74HC193DRJ
  • SN74HC193DRW
  • SN74HC193DRFK

CAD (KiCad official)

  • Symbol: SN74HC193DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 6ce6f3e3f359c50c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF