Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

TPS5450QDDARQ1

Texas Instruments · DC-DC Converters · SOIC-8-EP

TPS5450QDDARQ1 from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT passive Boost capacitor connection for high-side FET gate driver; connect 0.01 μF low-ESR capacitor between this pin and PH pin.
2 NC unconnected No internal connection.
3 NC unconnected No internal connection.
4 VSENSE input Feedback voltage input for output voltage regulation; connect to resistive divider network on output voltage.
5 ENA input On/off control input; device stops switching when voltage below 0.5 V; float pin to enable device.
6 GND power_in Ground reference and return path for device; must be connected to thermal pad for proper operation.
7 VIN power_in Input supply voltage (5.5 V to 36 V); must be bypassed to GND with high-quality low-ESR ceramic capacitor located close to device package.
8 PH output Switching node output; source of high-side power MOSFET; connect to external inductor and catch diode.
9 PowerPAD power_in Exposed thermal pad connected to ground; must be soldered to PCB ground plane for proper device operation and thermal management.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

CAD (KiCad official)

  • Symbol: TPS5450QDDARQ1
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: tps5450qddarq1-etched.step / tps5450qddarq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps5450qddarq1.step / tps5450qddarq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 54c3f25cadbdcce5, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF