component
MCP73871-2CAI
Public Made by Adomby adom
MICROCHIP TECHNOLOGY Global Sourcing Parts, QFN-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownMCP73871-2CAI
MICROCHIP TECHNOLOGY · Global Sourcing Parts · QFN-20(4x4)
MCP73871-2CAI from MICROCHIP TECHNOLOGY, in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | System output terminal that powers the system while the battery is charged independently; bypass to VSS with a minimum of 4.7 µF is recommended. |
| 2 | VPCC | input | Voltage proportional charge control input; supplying 1.23V or greater enables the feature, and connecting it to IN disables the feature. |
| 3 | SEL | input | Input source type selection: low for a USB port input, high for an AC-DC adapter input. |
| 4 | PROG2 | input | USB port input current limit selection when SEL is low: low = 100 mA, high = 500 mA. |
| 5 | THERM | bidirectional | Thermistor monitoring input and bias current for the battery cell temperature monitor. |
| 6 | PG | output | Power Good status output (open-drain); low when the input is above the UVLO threshold and greater than the battery voltage. |
| 7 | STAT2 | output | Charge Status Output 2 (open-drain) for an LED or a pull-up resistor to a host microcontroller. |
| 8 | STAT1/LBO | output | Charge Status Output 1 (open-drain); functions as the low battery output indicator when VBAT > VIN. |
| 9 | TE | input | Timer Enable input; enables the safety timer when active-low. |
| 10 | VSS | power_in | Battery management 0V reference, connected to the negative terminal of the battery, system load and input supply. |
| 11 | VSS | power_in | Battery management 0V reference, connected to the negative terminal of the battery, system load and input supply. |
| 12 | PROG3 | bidirectional | Termination set point for both AC-DC adapter and USB port. |
| 13 | PROG1 | bidirectional | Fast charge current regulation setting with SEL high and preconditioning set point for both USB port and AC-DC adapter; maximum constant charge current is set by a resistor from PROG1 to VSS. |
| 14 | VBAT | power_in | Battery positive input and output connection; bypass to VSS with a minimum of 4.7 µF to ensure loop stability when the battery is disconnected. |
| 15 | VBAT | power_in | Battery positive input and output connection; bypass to VSS with a minimum of 4.7 µF to ensure loop stability when the battery is disconnected. |
| 16 | VBAT_SENSE | bidirectional | Battery voltage sense; connect to the positive battery terminal, where a precision internal sense regulates the final voltage to VREG. |
| 17 | CE | input | Device Charge Enable input; charging is enabled when CE is high. |
| 18 | IN | power_in | Power supply input; a supply of VREG + 0.3V to 6V is recommended, bypassed to VSS with a minimum of 4.7 µF. |
| 19 | IN | power_in | Power supply input; a supply of VREG + 0.3V to 6V is recommended, bypassed to VSS with a minimum of 4.7 µF. |
| 20 | OUT | power_out | System output terminal that powers the system while the battery is charged independently; bypass to VSS with a minimum of 4.7 µF is recommended. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MICROCHIP TECHNOLOGY |
| Package | QFN-20(4x4) |
| Category | Global Sourcing Parts |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature Range | TA | -65 | 150 | °C | 4 | ||
| Specified Temperature Range | TA | -40 | 85 | °C | 8 | ||
| Operating Temperature Range | TJ | -40 | 125 | °C | 8 | ||
| Supply Voltage (absolute maximum) | VIN | 7 | V | 4 | |||
| All Inputs and Outputs w.r.t. VSS | -0.3 | V | w.r.t. VSS; VDD = VIN or VBAT | 4 | |||
| Supply Voltage | VIN | 6 | V | 4 | |||
| Supply Current - Charging | ISS | 2500 | 3750 | µA | Charging | 4 | |
| Supply Current - Charge Complete | ISS | 260 | 350 | µA | Charge Complete | 4 | |
| Supply Current - Standby | ISS | 180 | 300 | µA | Standby | 4 | |
| Supply Current - Shutdown | ISS | 28 | 50 | µA | (VDD < VBAT, 100 mV or VDD < VSTOP) | 4 | |
| Regulated Charge Voltage Tolerance | VRTOL | -0.5 | 0.5 | % | TA = +25°C | 4 | |
| Regulated Charge Voltage Tolerance | VRTOL | -0.75 | 0.75 | % | TA = -5°C to +55°C | 4 | |
| Line Regulation | 0.08 | 0.2 | %/V | VDD = [VREG(typical) + 1V] to 6V, IOUT = 10 mA | 4 | ||
| Load Regulation | 0.08 | 0.18 | % | IOUT = 10 mA to 150 mA, VDD = [VREG(typical) + 1V] | 4 | ||
| AC-Adapter Fast Charge Current | IREG | 90 | 100 | 110 | mA | PROG1 = 10 kΩ, TA = -5°C to +55°C, SEL = High | 5 |
| AC-Adapter Fast Charge Current | IREG | 900 | 1000 | 1100 | mA | PROG1 = 1 kΩ, TA = -5°C to +55°C, SEL = High | 5 |
| USB Fast Charge Current | IREG | 80 | 90 | 100 | mA | PROG2 = Low, SEL = Low, (Note 2), TA = -5°C to +55°C | 5 |
| USB Fast Charge Current | IREG | 400 | 450 | 500 | mA | PROG2 = High, SEL = Low, (Note 2), TA = -5°C to +55°C | 5 |
| USB-Port Supply Current Limit | ILIMIT_USB | 80 | 90 | 100 | mA | PROG2 = Low, SEL = Low, TA = -5°C to +55°C | 5 |
| USB-Port Supply Current Limit | ILIMIT_USB | 400 | 450 | 500 | mA | PROG2 = High, SEL = Low, TA = -5°C to +55°C | 5 |
| AC-DC Adapter Current Limit | ILIMIT_AC | 1500 | 1650 | 1800 | mA | SEL = High, TA = -5°C to +55°C | 5 |
| VPCC Input Threshold Tolerance | VRTOL | -3 | 3 | % | 5 | ||
| Input Leakage Current (VPCC) | ILK | 0.01 | 1 | µA | VVPCC = VDD | 5 | |
| Precondition Current Ratio | IPREG/IREG | 7.5 | 10 | 12.5 | % | PROG1 = 1.0 kΩ to 10 kΩ, TA = -5°C to +55°C | 5 |
| Precondition Current Threshold Ratio | VPTH/VREG | 69 | 72 | 75 | % | VBAT Low-to-High | 5 |
| Charge Termination Current Ratio | ITERM | 75 | 100 | 125 | mA | PROG3 = 10 kΩ, TA = -5°C to +55°C | 5 |
| Charge Termination Current Ratio | ITERM | 7.5 | 10 | 12.5 | mA | PROG3 = 100 kΩ, TA = -5°C to +55°C | 5 |
| Output Reverse Leakage Current | IDISCHARGE | 30 | 40 | µA | Shutdown (VBAT < VDD < VUVLO) | 6 | |
| Output Reverse Leakage Current | IDISCHARGE | -6 | -13 | µA | Charge Complete | 6 | |
| Sink Current | ISINK | 16 | 35 | mA | 6 | ||
| Low Output Voltage | VOL | 0.4 | 1 | V | ISINK = 4 mA | 6 | |
| Input Leakage Current (Status Indicators) | ILK | 0.01 | 1 | µA | High Impedance, VDD on pin | 6 | |
| PROG1 Charge Impedance Range | RPROG | 1 | 20 | kΩ | 6 | ||
| PROG3 Termination Impedance Range | RPROG | 5 | 100 | kΩ | 6 | ||
| PROG2 Input High Voltage Level | VIH | 1.8 | V | 6 | |||
| PROG2 Input Low Voltage Level | VIL | 0.8 | V | 6 | |||
| PROG2 Input Leakage Current | ILK | 0.01 | 1 | µA | VPROG2 = VDD | 6 | |
| Timer Enable (TE) Input High Voltage Level | VIH | 1.8 | V | Note 1 | 6 | ||
| Timer Enable (TE) Input Low Voltage Level | VIL | 0.8 | V | Note 1 | 6 | ||
| Chip Enable (CE) Input High Voltage Level | VIH | 1.8 | V | 7 | |||
| Chip Enable (CE) Input Low Voltage Level | VIL | 0.8 | V | 7 | |||
| Input Source Selection (SEL) Input High Voltage Level | VIH | 1.8 | V | 7 | |||
| Input Source Selection (SEL) Input Low Voltage Level | VIL | 0.8 | V | 7 | |||
| Thermistor Current Source | ITHERM | 47 | 50 | 53 | µA | 2 kΩ < RTHERM < 50 kΩ | 7 |
| Upper Trip Threshold | VT1 | 1.2 | 1.24 | 1.26 | V | VT1 Low-to-High | 7 |
| Lower Trip Threshold | VT2 | 0.23 | 0.25 | 0.27 | V | VT2 High-to-Low | 7 |
| UVLO Start Delay | tSTART | 5 | ms | VDD Low-to-High | 8 | ||
| Transition Time Out of Precondition | tDELAY | 10 | ms | VBAT < VPTH to VBAT > VPTH | 8 | ||
| Current Rise Time Out of Precondition | tRISE | 10 | ms | IOUT Rising to 90% of IREG | 8 | ||
| Precondition Comparator Filter Time | tPRECON | 0.4 | 1.3 | 3.2 | ms | Average VBAT Rise/Fall | 8 |
| Termination Comparator Filter Time | tTERM | 0.4 | 1.3 | 3.2 | ms | Average IOUT Falling | 8 |
| Charge Comparator Filter Time | tCHARGE | 0.4 | 1.3 | 3.2 | ms | Average VBAT Falling | 8 |
| Thermistor Comparator Filter Time | tTHERM | 0.4 | 1.3 | 3.2 | ms | Average THERM Rise/Fall | 8 |
| Elapsed Timer Period (6-hour option, code C) | tELAPSED | 5.4 | 6 | 6.6 | Hours | 8 | |
| ESD Human Body Model | 4 | kV | Human Body Model (1.5 kΩ in series with 100 pF) | 4 | |||
| ESD Machine Model | 300 | V | Machine Model (200 pF, no series resistance) | 4 | |||
| Thermal Resistance, 20LD-QFN 4x4 | JA | 50 | °C/W | 4-Layer JC51-7 Standard Board, Natural Convection | 8 | ||
| Thermal Resistance, 20LD-QFN 4x4 (junction-to-case) | JC | 8 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
MCP73871-2CAI - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: QFN-20(4x4) (KiCad packages3D, STEP)
- 3D model files:
mcp73871-2cai-etched.step/mcp73871-2cai-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp73871-2cai.step/mcp73871-2cai.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MICROCHIP TECHNOLOGY datasheet (36 pp, sha256
56654f56a8ac83ad, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).