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DAC43204RTER
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC43204RTER
Texas Instruments · Digital To Analog Converters (DAC) · WQFN-16(3x3)
DAC43204RTER from Texas Instruments, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB3 | input | Voltage feedback pin for channel 3; connect to OUT3 in voltage-output mode and leave unconnected in current-output mode to minimize leakage current. |
| 2 | OUT3 | output | Analog output voltage from DAC channel 3. |
| 3 | OUT2 | output | Analog output voltage from DAC channel 2. |
| 4 | FB2 | input | Voltage feedback pin for channel 2; connect to OUT2 in voltage-output mode and leave unconnected in current-output mode to minimize leakage current. |
| 5 | GPIO/SDO | bidirectional | General-purpose I/O configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS; for STATUS and SDO use an external pullup to the IO voltage, and if unused tie to VDD or AGND through a resistor. |
| 6 | SCL/SYNC | bidirectional | I2C serial interface clock or SPI chip select input; must be connected to the IO voltage through an external pullup resistor and can ramp up before VDD. |
| 7 | A0/SDI | input | Address configuration pin for I2C (connect to VDD, AGND, SDA, or SCL) or serial data input for SPI; need not be pulled up or down and can ramp up before VDD. |
| 8 | SDA/SCLK | bidirectional | Bidirectional I2C serial data bus or SPI clock input; must be pulled up to the IO voltage in I2C mode and can ramp up before VDD. |
| 9 | FB1 | input | Voltage feedback pin for channel 1; connect to OUT1 in voltage-output mode and leave unconnected in current-output mode to minimize leakage current. |
| 10 | OUT1 | output | Analog output voltage from DAC channel 1. |
| 11 | OUT0 | output | Analog output voltage from DAC channel 0. |
| 12 | FB0 | input | Voltage feedback pin for channel 0; connect to OUT0 in voltage-output mode and leave unconnected in current-output mode to minimize leakage current. |
| 13 | CAP | power_out | External bypass capacitor for the internal LDO; connect approximately 1.5 µF between CAP and AGND (CCAP 0.5 to 15 µF). |
| 14 | AGND | power_in | Ground reference point for all circuitry on the device. |
| 15 | VDD | power_in | Positive supply voltage, 1.7 V to 5.5 V recommended operating range, referenced to AGND. |
| 16 | VREF | power_in | External reference input; connect approximately 0.1 µF to AGND, use a pullup to VDD when unused, and must not ramp up before VDD. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16(3x3) |
| Category | Data Acquisition |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral nonlinearity (8-bit) | INL | -1 | 1 | LSB | 5 | ||
| Differential nonlinearity | DNL | -1 | 1 | LSB | 5 | ||
| Current output integral nonlinearity | INL | -1 | 1 | LSB | DAC codes between 0d and 255d | 7 | |
| Current output differential nonlinearity | DNL | -1 | 1 | LSB | DAC codes between 0d and 255d | 7 | |
| Offset error (VDD 1.7 V to 2.7 V) | -0.75 | 0.3 | 0.75 | %FSR | 1.7 V ≤ VDD < 2.7 V, FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution, 2d for 8-bit resolution | 5 | |
| Offset error (VDD 2.7 V to 5.5 V) | -0.5 | 0.25 | 0.5 | %FSR | 2.7 V ≤ VDD ≤ 5.5 V, FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution, 2d for 8-bit resolution | 5 | |
| Offset-error temperature coefficient | -0.0003 | 0.0003 | %FSR/°C | FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution, 2d for 8-bit resolution | 5 | ||
| Gain error | -0.5 | 0.25 | 0.5 | %FSR | Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution | 5 | |
| Gain-error temperature coefficient | -0.0008 | 0.0008 | %FSR/°C | Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution | 5 | ||
| Full-scale error (VDD 1.7 V to 2.7 V) | -1 | 1 | %FSR | 1.7 V ≤ VDD < 2.7 V, DAC at full-scale | 5 | ||
| Full-scale error (VDD 2.7 V to 5.5 V) | -0.5 | 0.5 | %FSR | 2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale | 5 | ||
| Full-scale-error temperature coefficient | -0.0008 | 0.0008 | %FSR/°C | DAC at full-scale | 5 | ||
| Zero-code error temperature coefficient | -10 | 10 | µV/°C | Code 0d into DAC | 5 | ||
| Current output offset error | -1 | 1 | %FSR | DAC at midscale | 7 | ||
| Current output gain error | -1.3 | 1.3 | %FSR | DAC codes between 0d and 255d | 7 | ||
| DAC output impedance (VFB), internal reference gain 1.5x/2x or external reference gain 1x | ZO | 400 | 500 | 600 | kΩ | DAC output enabled, internal reference (gain = 1.5x or 2x) or external reference at VDD (gain = 1x), the VREF pin is not shorted to VDD | 6 |
| DAC output impedance (VFB), internal VREF gain 3x/4x | ZO | 325 | 400 | 485 | kΩ | DAC output enabled, internal VREF, gain = 3x or 4x | 6 |
| Internal reference initial accuracy | 1.1979 | 1.212 | 1.224 | V | TA = 25°C | 9 | |
| Recommended positive supply voltage VDD | VDD | 1.7 | 5.5 | V | Positive supply voltage to ground (AGND) | 4 | |
| Recommended external reference voltage VREF | VREF | 1.7 | V | External reference to ground (AGND); maximum is VDD | 4 | ||
| Digital input high voltage | VIH | 1.62 | V | 1.7 V < VDD ≤ 5.5 V | 4 | ||
| Digital input low voltage | VIL | 0.4 | V | 4 | |||
| External capacitor on CAP pin | CCAP | 0.5 | 15 | µF | 4 | ||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Supply voltage VDD to AGND | VDD | -0.3 | 6 | V | 4 | ||
| Digital inputs to AGND | -0.3 | V | Maximum is VDD + 0.3 V | 4 | |||
| CAP to AGND | -0.3 | 1.65 | V | 4 | |||
| VFBX to AGND | -0.3 | V | Maximum is VDD + 0.3 V | 4 | |||
| VOUTX to AGND | -0.3 | V | Maximum is VDD + 0.3 V | 4 | |||
| VREF external reference to AGND | VREF | -0.3 | V | Maximum is VDD + 0.3 V | 4 | ||
| Current into any pin except the OUTx pins | -10 | 10 | mA | 4 | |||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Zero-code error, external reference | 6 | 12 | mV | Code 0d into DAC, external reference, VDD = 5.5 V | 5 | ||
| Zero-code error, internal reference | 6 | 15 | mV | Code 0d into DAC, internal VREF, gain = 4x, VDD = 5.5 V | 5 | ||
| Capacitive load, phase margin 30°, RL infinite | CL | 200 | pF | RL = infinite, phase margin = 30° | 5 | ||
| Capacitive load, phase margin 30° | CL | 1000 | pF | Phase margin = 30° | 5 | ||
| Output voltage range | 0 | V | Reference tied to VDD; maximum is VDD | 5 | |||
| Output voltage settling time | tsett | 20 | µs | 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V | 5 | ||
| Initial reference temperature coefficient | 50 | ppm/°C | Reference output temperature coefficient | 9 | |||
| VREF input impedance | 192 | kΩ/ch | Impedances for the DAC channels are connected in parallel | 9 | |||
| Junction-to-ambient thermal resistance | RθJA | 49 | °C/W | RTE (WQFN) 16 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 50 | °C/W | RTE (WQFN) 16 pins | 4 | ||
| Junction-to-board thermal resistance | RθJB | 24.1 | °C/W | RTE (WQFN) 16 pins | 4 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 8.7 | °C/W | RTE (WQFN) 16 pins | 4 | ||
| Junction-to-top characterization parameter | ΨJT | 1.1 | °C/W | RTE (WQFN) 16 pins | 4 | ||
| Junction-to-board characterization parameter | ΨJB | 24.1 | °C/W | RTE (WQFN) 16 pins | 4 | ||
| Supply current per channel, ±25 µA range, full scale | IDD | 42 | 50 | µA/ch | Normal operation, DACs at full scale, ±25-µA output range, digital pins static | 7 | |
| Supply current per channel, ±50 µA range, full scale | IDD | 56 | 70 | µA/ch | Normal operation, DACs at full scale, ±50-µA output range, digital pins static | 7 | |
| Supply current per channel, ±125 µA range, full scale | IDD | 98 | 120 | µA/ch | Normal operation, DACs at full scale, ±125-µA output range, digital pins static | 7 | |
| Supply current per channel, ±250 µA range, full scale | IDD | 167 | 200 | µA/ch | Normal operation, DACs at full scale, ±250-µA output range, digital pins static | 7 | |
| Supply current per channel, voltage output | IDD | 150 | µA/ch | Normal operation, DACs at full scale, digital pins static, external reference at VDD but the VREF pin is not shorted to VDD | 6 | ||
| Power-down current, sleep mode, external reference at 5.5 V | IDD | 28 | µA | DAC in sleep mode, internal reference powered down, external reference at 5.5 V | 9 | ||
| Power-down current, sleep mode, internal reference enabled | IDD | 10 | µA | DAC in sleep mode, internal reference enabled, additional current through internal reference | 9 | ||
| Power-down current, DAC channels enabled, internal reference per channel | IDD | 12.5 | µA | DAC channels enabled, internal reference enabled, additional current through internal reference per DAC channel in voltage-output mode | 9 | ||
| Pin capacitance | 10 | pF | Per pin | 9 |
CAD (KiCad official)
- Symbol:
DAC43204RTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
dac43204rter-etched.step/dac43204rter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac43204rter.step/dac43204rter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (83 pp, sha256
79cbaf6418c48bb3, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).