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74LVT14PW

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Nexperia Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74LVT14PW

Nexperia · Inverters · TSSOP-14

74LVT14PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input of inverter 1; the input has Schmitt-trigger thresholds and bus hold, so it needs no external pull-up to define an unused state.
2 1Y output Data output of inverter 1, the inverted logic level of input 1A.
3 2A input Data input of inverter 2; the input has Schmitt-trigger thresholds and bus hold, so it needs no external pull-up to define an unused state.
4 2Y output Data output of inverter 2, the inverted logic level of input 2A.
5 3A input Data input of inverter 3; the input has Schmitt-trigger thresholds and bus hold, so it needs no external pull-up to define an unused state.
6 3Y output Data output of inverter 3, the inverted logic level of input 3A.
7 GND power_in Ground reference at 0 V for all voltages on the device.
8 4Y output Data output of inverter 4, the inverted logic level of input 4A.
9 4A input Data input of inverter 4; the input has Schmitt-trigger thresholds and bus hold, so it needs no external pull-up to define an unused state.
10 5Y output Data output of inverter 5, the inverted logic level of input 5A.
11 5A input Data input of inverter 5; the input has Schmitt-trigger thresholds and bus hold, so it needs no external pull-up to define an unused state.
12 6Y output Data output of inverter 6, the inverted logic level of input 6A.
13 6A input Data input of inverter 6; the input has Schmitt-trigger thresholds and bus hold, so it needs no external pull-up to define an unused state.
14 VCC power_in Positive supply voltage, specified from 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2.7 3.6 V 4
input voltage VI 0 5.5 V 4
HIGH-level output current IOH -20 mA 4
LOW-level output current IOL 32 mA 4
ambient temperature in free air Tamb -40 85 °C 4
input transition rise and fall rate Δt/ΔV 0 10 ns/V output enabled 4
supply voltage VCC -0.5 4.6 V 4
input voltage VI -0.5 7 V 4
output voltage VO -0.5 7 V output in OFF or HIGH state 4
input clamping current IIK -50 mA VI < 0 V 4
output clamping current IOK -50 mA VO < 0 V 4
output current IO 64 mA output in LOW state 4
output current IO -32 mA output in HIGH state 4
storage temperature Tstg -65 150 °C 4
junction temperature Tj 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +85 °C 4
positive-going threshold voltage VT+ 1.5 1.7 2 V VCC = 3.3 V; see Fig. 4 5
negative-going threshold voltage VT- 0.9 1.1 1.3 V VCC = 3.3 V; see Fig. 4 5
hysteresis voltage VH 0.4 0.6 V VCC = 3.3 V; see Fig. 4 5
input clamping voltage VIK -1.2 V VCC = 2.7 V; IIK = -18 mA 5
HIGH-level output voltage VOH 2.4 V VCC = 2.7 V; IOH = -6 mA 5
HIGH-level output voltage VOH 2 V VCC = 3.0 V; IOH = -20 mA 5
LOW-level output voltage VOL 0.2 V VCC = 2.7 V; IOL = 100 μA 5
LOW-level output voltage VOL 0.5 V VCC = 2.7 V; IOL = 24 mA 5
input leakage current II 10 μA VCC = 0 V or 3.6 V; VI = 5.5 V 5
input leakage current II -1 1 μA VCC = 3.6 V; VI = VCC or GND 5
power-off leakage current IOFF -100 100 μA VCC = 0 V; VI or VO = 0 V to 4.5 V 5
supply current outputs HIGH ICC 0.02 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A 5
supply current outputs LOW ICC 1.5 3 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A 5
additional supply current per input pin ΔICC 0.2 mA VCC = 3.0 V to 3.6 V; one input = VCC - 0.6 V and other inputs at VCC or GND 5
input capacitance CI 3 pF VI = 0 V or 3.0 V 5
LOW to HIGH propagation delay tPLH 6.9 ns nA to nY; see Fig. 5; VCC = 2.7 V 5
LOW to HIGH propagation delay tPLH 1 3.8 5.7 ns nA to nY; see Fig. 5; VCC = 3.3 V + 0.3 V 5
HIGH to LOW propagation delay tPHL 4.1 ns nA to nY; see Fig. 5; VCC = 2.7 V 5
HIGH to LOW propagation delay tPHL 1 3.2 4.5 ns nA to nY; see Fig. 5; VCC = 3.3 V + 0.3 V 5

CAD (KiCad official)

  • Symbol: 74LVT14PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvt14pw-etched.step / 74lvt14pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvt14pw.step / 74lvt14pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 0a4240fb0a6a094c, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF