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SN75LVDS31PW
Public Made by Adomby adom
Texas Instruments LVDS ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN75LVDS31PW
Texas Instruments · LVDS ICs · TSSOP-16
SN75LVDS31PW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Driver 1 LVTTL logic input, which must meet VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 2 | 1Y | output | Driver 1 non-inverting LVDS output, which delivers a minimum differential output magnitude of 247 mV into a 100-Ω load when enabled and goes high impedance when disabled or with VCC = 0. |
| 3 | 1Z | output | Driver 1 inverting LVDS output, which forms a differential pair with 1Y and goes high impedance when disabled or with VCC = 0. |
| 4 | G | input | Driver enable input used with the complementary enable G, where per the function table the outputs go high impedance when G is low and G is high. |
| 5 | 2Z | output | Driver 2 inverting LVDS output, which forms a differential pair with 2Y and goes high impedance when disabled or with VCC = 0. |
| 6 | 2Y | output | Driver 2 non-inverting LVDS output, which delivers a minimum differential output magnitude of 247 mV into a 100-Ω load when enabled and goes high impedance when disabled or with VCC = 0. |
| 7 | 2A | input | Driver 2 LVTTL logic input, which must meet VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 8 | GND | power_in | Network ground terminal, to which all voltages except differential I/O bus voltages are referenced. |
| 9 | 3A | input | Driver 3 LVTTL logic input, which must meet VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 10 | 3Y | output | Driver 3 non-inverting LVDS output, which delivers a minimum differential output magnitude of 247 mV into a 100-Ω load when enabled and goes high impedance when disabled or with VCC = 0. |
| 11 | 3Z | output | Driver 3 inverting LVDS output, which forms a differential pair with 3Y and goes high impedance when disabled or with VCC = 0. |
| 12 | G | input | Second driver enable input (complementary to G) that, together with pin 4, controls the high-impedance state of all four drivers per the function table. |
| 13 | 4Z | output | Driver 4 inverting LVDS output, which forms a differential pair with 4Y and goes high impedance when disabled or with VCC = 0. |
| 14 | 4Y | output | Driver 4 non-inverting LVDS output, which delivers a minimum differential output magnitude of 247 mV into a 100-Ω load when enabled and goes high impedance when disabled or with VCC = 0. |
| 15 | 4A | input | Driver 4 LVTTL logic input, which must meet VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 16 | VCC | power_in | Single 3.3-V supply, with a recommended operating range of 3 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN75LVDS31PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn75lvds31pw-etched.step/sn75lvds31pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn75lvds31pw.step/sn75lvds31pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
e919eba951d3c915, retrieved 2026-10-10, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).