component
PUMD15
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownPUMD15
Nexperia · Digital Transistors · SOT-363
PUMD15 from Nexperia, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND1 | power_in | GND (emitter) connection of TR1 (NPN) in the internal resistor-equipped double transistor. |
| 2 | I1 | input | Input (base) of TR1 (NPN); the datasheet gives the TR1 input voltage range as -10 V to 30 V. |
| 3 | O2 | output | Output (collector) of TR2 (PNP); the datasheet gives the TR2 input voltage range as -30 V to 10 V and the output current limit as 100 mA. |
| 4 | GND2 | power_in | GND (emitter) connection of TR2 (PNP) in the internal resistor-equipped double transistor. |
| 5 | I2 | input | Input (base) of TR2 (PNP); the datasheet gives the TR2 input voltage range as -30 V to 10 V. |
| 6 | O1 | output | Output (collector) of TR1 (NPN); the datasheet gives the output current limit as 100 mA and the collector-emitter voltage as 50 V maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| collector-base voltage | VCBO | 50 | V | open emitter | 3 | ||
| collector-emitter voltage | VCEO | 50 | V | open base | 3 | ||
| emitter-base voltage | VEBO | 10 | V | open collector | 3 | ||
| input voltage TR1 (NPN) | VI | -10 | 30 | V | TR1 (NPN) | 3 | |
| input voltage TR2 (PNP) | VI | -30 | 10 | V | TR2 (PNP) | 3 | |
| output current | IO | 100 | mA | 3 | |||
| total power dissipation, per transistor | Ptot | 200 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper [2] | 3 | ||
| total power dissipation, per device | Ptot | 300 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper [2] | 3 | ||
| junction temperature | Tj | 150 | °C | 3 | |||
| ambient temperature | Tamb | -65 | 150 | °C | 3 | ||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| thermal resistance from junction to ambient, per transistor | Rth(j-a) | 625 | K/W | in free air; FR4 PCB, single-sided copper [1] | 4 | ||
| thermal resistance from junction to ambient, per device | Rth(j-a) | 417 | K/W | in free air; FR4 PCB, single-sided copper [1] | 4 | ||
| collector-base breakdown voltage | V(BR)CBO | 50 | V | IC = 100 µA; IE = 0 A; Tamb = 25 °C [1] | 5 | ||
| collector-emitter breakdown voltage | V(BR)CEO | 50 | V | IC = 2 mA; IB = 0 A; Tamb = 25 °C [1] | 5 | ||
| collector-base cut-off current | ICBO | 100 | nA | VCB = 50 V; IE = 0 A; Tamb = 25 °C [1] | 5 | ||
| collector-emitter cut-off current | ICEO | 100 | nA | VCE = 30 V; IB = 0 A; Tamb = 25 °C [1] | 5 | ||
| collector-emitter cut-off current at high temperature | ICEO | 5 | µA | VCE = 30 V; IB = 0 A; Tj = 150 °C [1] | 5 | ||
| emitter-base cut-off current | IEBO | 900 | µA | VEB = 5 V; IC = 0 A; Tamb = 25 °C [1] | 5 | ||
| DC current gain | hFE | 30 | VCE = 5 V; IC = 10 mA; Tamb = 25 °C [1] | 5 | |||
| collector-emitter saturation voltage | VCEsat | 150 | mV | IC = 10 mA; IB = 0.5 mA; Tamb = 25 °C [1] | 5 | ||
| off-state input voltage | VI(off) | 1.1 | 0.5 | V | VCE = 5 V; IC = 100 µA; Tamb = 25 °C [1] | 5 | |
| on-state input voltage | VI(on) | 2.5 | 1.9 | V | VCE = 0.3 V; IC = 20 mA; Tamb = 25 °C [1] | 5 | |
| bias resistor 1 (input) | R1 | 3.3 | 4.7 | 6.1 | kΩ | 5 | |
| bias resistor ratio | R2/R1 | 0.8 | 1 | 1.2 | 5 | ||
| collector capacitance TR1 (NPN) | Cc | 2.5 | pF | VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C | 5 | ||
| collector capacitance TR2 (PNP) | Cc | 3 | pF | VCB = -10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C | 5 |
CAD (KiCad official)
- Symbol:
PUMD15 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
pumd15-etched.step/pumd15-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pumd15.step/pumd15.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
d7de88d21cc0fecf, retrieved 2026-10-19, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).