component
APM32F103TBU7
Public Made by Adomby adom
Geehy Microcontrollers (MCU/MPU/SOC), QFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAPM32F103TBU7
Geehy · Microcontrollers (MCU/MPU/SOC) · QFN-36(6x6)
APM32F103TBU7 from Geehy, in a QFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD_3 | power_in | Digital supply input for the I/O ports and the internal core regulator, specified at 2.0 V to 3.6 V. |
| 2 | OSC_IN | input | HXT crystal oscillator input (4-16 MHz); after reset this pin defaults to OSC_IN and can be switched in software to PD0. |
| 3 | OSC_OUT | output | HXT crystal oscillator output; after reset this pin defaults to OSC_OUT and can be switched in software to PD1. |
| 4 | NRST | bidirectional | Reset pin with a permanent internal pull-up of 32-49 kΩ; input low level max 0.8 V and input high level min 2 V. |
| 5 | VSSA | power_in | Analog ground for the ADC, reset block, RC oscillators and PLL; must be connected to VSS. |
| 6 | VDDA | power_in | Analog supply for the ADC, reset block, RC oscillators and PLL; must be connected to VDD, and must be 2.4 V to 3.6 V when the ADC is used. |
| 7 | PA0-WKUP | bidirectional | GPIO PA0 with WKUP wake-up input (rising edge exits standby), ADC12_IN0, USART2_CTS and TMR2_CH1_ETR alternates; not marked 5 V tolerant in the table. |
| 8 | PA1 | bidirectional | GPIO PA1 with ADC12_IN1, USART2_RTS and TMR2_CH2 alternates; not marked 5 V tolerant in the table. |
| 9 | PA2 | bidirectional | GPIO PA2 with ADC12_IN2, USART2_TX and TMR2_CH3 alternates; not marked 5 V tolerant in the table. |
| 10 | PA3 | bidirectional | GPIO PA3 with ADC12_IN3, USART2_RX and TMR2_CH4 alternates; not marked 5 V tolerant in the table. |
| 11 | PA4 | bidirectional | GPIO PA4 with ADC12_IN4, SPI1_NSS and USART2_CK alternates; not marked 5 V tolerant in the table. |
| 12 | PA5 | bidirectional | GPIO PA5 with ADC12_IN5 and SPI1_SCK alternates; not marked 5 V tolerant in the table. |
| 13 | PA6 | bidirectional | GPIO PA6 with ADC12_IN6, SPI1_MISO, TMR3_CH1 and TMR1_BKIN alternates; not marked 5 V tolerant in the table. |
| 14 | PA7 | bidirectional | GPIO PA7 with ADC12_IN7, SPI1_MOSI, TMR3_CH2 and TMR1_CH1N alternates; not marked 5 V tolerant in the table. |
| 15 | PB0 | bidirectional | GPIO PB0 with ADC12_IN8, TMR3_CH3 and TMR1_CH2N alternates; not marked 5 V tolerant in the table. |
| 16 | PB1 | bidirectional | GPIO PB1 with ADC12_IN9, TMR3_CH4 and TMR1_CH3N alternates; not marked 5 V tolerant in the table. |
| 17 | PB2 | bidirectional | 5 V tolerant GPIO PB2, also used as BOOT1 for boot mode selection. |
| 18 | VSS_1 | power_in | Ground pin for the I/O ring and digital logic; connect to board ground. |
| 19 | VDD_1 | power_in | Digital supply input for the I/O ring and digital logic, specified at 2.0 V to 3.6 V. |
| 20 | PA8 | bidirectional | 5 V tolerant GPIO PA8 with USART1_CK, TMR1_CH1 and MCO alternates. |
| 21 | PA9 | bidirectional | 5 V tolerant GPIO PA9 with USART1_TX and TMR1_CH2 alternates. |
| 22 | PA10 | bidirectional | 5 V tolerant GPIO PA10 with USART1_RX and TMR1_CH3 alternates. |
| 23 | PA11 | bidirectional | 5 V tolerant GPIO PA11 with USART1_CTS, USBDM, CAN_RX and TMR1_CH4 alternates; the datasheet reserves PA11/PA12 for USB when USB and CAN are used together. |
| 24 | PA12 | bidirectional | 5 V tolerant GPIO PA12 with USART1_RTS, USBDP, CAN_TX and TMR1_ETR alternates; the datasheet reserves PA11/PA12 for USB when USB and CAN are used together. |
| 25 | PA13 | bidirectional | 5 V tolerant GPIO PA13 whose default function after reset is the JTMS/SWDIO debug pin. |
| 26 | VSS_2 | power_in | Ground pin for the digital logic and I/O; connect to board ground. |
| 27 | VDD_2 | power_in | Digital supply input for the digital logic and I/O, specified at 2.0 V to 3.6 V. |
| 28 | PA14 | bidirectional | 5 V tolerant GPIO PA14 whose default function after reset is the JTCK debug clock (printed as SWCMU in the table). |
| 29 | PA15 | bidirectional | 5 V tolerant GPIO PA15 whose default function after reset is JTDI, with TMR2_CH1_ETR and SPI1_NSS alternates. |
| 30 | PB3 | bidirectional | 5 V tolerant GPIO PB3 whose default function after reset is JTDO, with TRACESWO, TMR2_CH2 and SPI1_SCK alternates. |
| 31 | PB4 | bidirectional | 5 V tolerant GPIO PB4 whose default function after reset is NJTRST, with TMR3_CH1 and SPI1_MISO alternates. |
| 32 | PB5 | bidirectional | GPIO PB5 with I2C1_SMBAI, TMR3_CH2 and SPI1_MOSI alternates; not marked 5 V tolerant in the table. |
| 33 | PB6 | bidirectional | 5 V tolerant GPIO PB6 with I2C1_SCL, I2C3_SCL, TMR4_CH1 and USART1_TX alternates. |
| 34 | PB7 | bidirectional | 5 V tolerant GPIO PB7 with I2C1_SDA, I2C3_SDA, TMR4_CH2 and USART1_RX alternates. |
| 35 | BOOT0 | input | Boot mode select input that, together with BOOT1 (PB2), selects boot from user flash, system memory or internal SRAM. |
| 36 | VSS_3 | power_in | Ground pin for the digital logic and I/O; connect to board ground. |
| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Geehy |
| Package | QFN-36(6x6) |
| Category | Embedded Processors & Controllers |
| Pins | 37 |
CAD (KiCad official)
- Symbol:
APM32F103TBU7 - Footprint:
Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm - 3D model: QFN-36(6x6) (KiCad packages3D, STEP)
- 3D model files:
apm32f103tbu7-etched.step/apm32f103tbu7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);apm32f103tbu7.step/apm32f103tbu7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Geehy datasheet (84 pp, sha256
1fb9f43ef8119b4c, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).